Utilizing slow ASIC logic BIST to preserve timing integrity...

Details Utilizing slow ASIC logic BIST to preserve timing integrity... Utilizing slow ASIC logic BIST to preserve timing integrity...

2005-05-31

2005-05-31

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S739000, C714S732000, C714S728000, C326S096000, C324S763010

Reexamination Certificate

active

06901543

ABSTRACT:
A logic built-in self-test controller is disclosed. The invention, in its various aspects and embodiments, is a built-in self-test controller capable of performing a logic built-in self-test at a test frequency at least as slow as a slowest frequency of a plurality of timing domains to undergo the logic built-in self-test. A method for performing a built-in self-test on an integrated circuit device.

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