Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-03-23
2003-06-24
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S626000, C438S637000, C438S687000, C438S700000
Reexamination Certificate
active
06583053
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of fabricating copper interconnects in semiconductor devices and more specifically to the use of a sacrificial layer to facilitate metallization for small features.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any liner/barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. A thin liner/barrier material is then deposited over the structure followed by copper deposition over the liner/barrier material. Then, the copper and liner/barrier material are chemically-mechanically polished to remove the material from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
The most practical technique for forming copper interconnects is electrochemical deposition (ECD). In this process, after the liner/barrier material is deposited, a seed layer of copper is deposited. Then, ECD is used to deposit copper over the seed layer. At this time, the only practical method for forming the copper seed layer is ionized sputtering. However, sputtering is a line-of-sight technique that has poor step coverage. The major problem for a sputtered film is the overhang near the top of the small features. As a result, an overhang
18
of the seed
16
material occurs at the top of a trench or via
12
as illustrated in FIG.
1
. During the subsequent copper ECD, the overhang causes premature closing of the trench or via
12
, leaving behind seams and/or voids in the copper fill material.
SUMMARY OF THE INVENTION
The invention is a method of fabricating a copper interconnect using a sacrificial layer. A polish stop layer is formed over a dielectric layer. A sacrificial layer is formed over the polish stop layer. A trench is etched in the sacrificial layer, the polish stop layer, and the dielectric layer. A sputter etch of the sacrificial layer is used to create a wider opening at a top of the sacrificial layer than at a top of the dielectric layer. A barrier layer and copper seed layer are formed. The trench is then filled with copper. CMP is used to remove the excess copper and barrier layer, stopping on the polish stop layer.
An advantage of the invention is providing an improved fill process that eliminates the formation of seams in the fill material.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5933754 (1999-08-01), Mathews et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6211071 (2001-04-01), Lukanc et al.
patent: 6274483 (2001-08-01), Chang et al.
patent: 6294457 (2001-09-01), Liu
patent: 11251271 (1999-09-01), None
Jin Changming
Lu Jiong-Ping
Permana David
Brady III W. James
Garner Jacqueline J.
Jr. Carl Whitehead
Pham Thanhha
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