Upward plug process for metal via holes

Details Upward plug process for metal via holes Upward plug process for metal via holes

1994-07-05

1995-01-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437190, 437195, H01L 2144, H01L 2148

Patent

active

053858689

ABSTRACT:
A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

REFERENCES:
patent: 5006484 (1991-04-01), Harada
patent: 5082801 (1992-01-01), Nagata
patent: 5093710 (1992-03-01), Higuchi
VLSI Technology, S. M. Sze, McGraw-Hill Book Co. p. 409, 1988.

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