Upward plug filled via hole device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257751, 257915, 437190, 428332, 428688, 428704, 428650, 428660, H01L 2352, H01L 2912, B32B 1504, B32B 904

Patent

active

057264970

ABSTRACT:
A method of manufacture of a semiconductor device on a silicon semiconductor substrate comprises formation of a first stress layer on the semiconductor substrate, formation of an interconnect layer over the first stress layer, formation of a second stress layer on the interconnect layer, formation of an inter-metal dielectric (IMD) layer over the second stress layer, patterning and etching a via opening through the inter-metal dielectric layer and the second stress layer exposing a contact area on the surface of the metal interconnect layer, and heating the device at a temperature sufficient to squeeze the metal interconnect layer up into the via.

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patent: 4782380 (1988-11-01), Shankar et al.
patent: 5082801 (1992-01-01), Nagata
patent: 5084414 (1992-01-01), Manley et al.
patent: 5200360 (1993-04-01), Bradbury
patent: 5360994 (1994-11-01), Wolters
Sze, VLSI Technology, McGraw-Hill Book Company, p. 409, (1988) no month.

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