Ultra-thin Si channel CMOS with improved series resistance

Details Ultra-thin Si channel CMOS with improved series resistance Ultra-thin Si channel CMOS with improved series resistance

2006-03-28

2006-03-28

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S595000

Reexamination Certificate

active

07018891

ABSTRACT:
Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.

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