Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With bumps on ends of lead fingers to connect to semiconductor
Reexamination Certificate
2002-01-29
2002-12-24
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With bumps on ends of lead fingers to connect to semiconductor
C257S666000, C257S696000, C257S698000, C257S672000, C257S671000, C257S670000, C257S784000, C257S786000, C257S687000, C257S668000
Reexamination Certificate
active
06498389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packaging technology.
More particularly, the present invention relates to an ultra-thin semiconductor package having a thickness of 0.5 mm using a film-type adhesive support tape.
2. Description of Related Art
Recently, as the supply of various portable electronic devices such as digital cameras, MP3 players, handheld personal computers (HPC) and personal digital assistants (PDA) expands, new technologies are required to produce semiconductor packages having a smaller and thinner structure.
FIG. 1
illustrates an end view of a conventional semiconductor package device
10
using a lead frame. The package device
10
includes a semiconductor chip
1
and a lead frame
2
. The lead frame
2
includes a plurality of leads
4
and a die pad
3
to which the semiconductor chip
1
is attached using an adhesive
5
. Each one of the plurality of leads
4
is connected to semiconductor chip
1
by a bonding wire
6
and further includes an inner lead
4
a encapsulated by a molding body
7
and an outer lead
4
b exposed from the molding body
7
and having a structure suitable for mounting on an external device.
In conventional package
10
, total thickness of the package
10
is determined by the thickness of the semiconductor chip
1
, the die pad
3
, the adhesive
5
and a loop in each bonding wire
6
. The thickness of a semiconductor chip
1
manufactured from an 8-inch wafer, the adhesive
5
, the wire loop and the die pad
3
are generally 300 &mgr;m, 50 &mgr;m, 80-100 &mgr;m and 100-150 &mgr;m, respectively. Due to the thickness of the molding body
7
above and below the semiconductor chip
1
and a stand-off of the outer lead
4
b,
it is impossible to embody a conventional package having a thickness of less than 0.5 mm.
FIG. 2
illustrates an end view of a conventional semiconductor package device having a lead-on-chip (LOC) structure. In a package
20
shown in
FIG. 2
, a plurality of electrode pads are formed in the center of an active surface of a semiconductor chip
11
, and an inner lead
14
a
of each one of a plurality of leads
14
is directly attached to the periphery of the active surface. In this structure, each lead
14
is mounted on the semiconductor chip
11
. Each inner lead
14
a
is attached to a chip surface by an adhesive
13
and is electrically connected to an electrode pad of the semiconductor chip
11
by a bonding wire
16
. The semiconductor chip
11
, inner leads
14
a
and bonding wires
16
are encapsulated by a molding body
17
. An outer lead
14
b
of each of the plurality of leads
14
is exposed from the molding body
17
.
Disadvantageously, although the inner lead
14
a
in the package
20
of
FIG. 2
functions similar to the die pad
3
in the package
10
of
FIG. 1
, total thickness of a package cannot be reduced due to the wire loop
16
above the inner lead
14
a
. Further, although conventional semiconductor packages may be made thinner by reducing the thickness of the semiconductor chip and/or the lead frame, such thinner elements are less durable and may be easily broken during routine handling.
SUMMARY OF THE INVENTION
According to a feature of an embodiment of the present invention, there is provided an ultra-thin semiconductor package device using plastic package technology.
According to another feature of an embodiment of the present invention, there is provided a semiconductor package device having a thickness of less than 0.5 mm capable of maintaining proper thickness of a semiconductor chip or a lead frame.
According to an aspect of an embodiment of the present invention, a semiconductor package device uses a heat-resistant support tape instead of a die pad as a lead frame. The support tape is preferably a film-type adhesive tape. The semiconductor package device includes a semiconductor chip having an active surface in which a plurality of electrode pads are formed and a bottom surface opposite of the active surface, a plurality of lead frames connected to each electrode pad of the semiconductor chip, including an inner lead having an upper surface, wherein the height of the upper surface is equal to the height of the active surface (i.e., the two surfaces are aligned), a plurality of bonding wires, each electrically connecting one electrode pad of the semiconductor chip with an associated inner lead, and a molding body encapsulating the semiconductor chip, the support tape and the plurality of bonding wires, wherein the heat-resistant support tape is attached to the upper surface of the inner lead and the active surface of the semiconductor chip and supports the inner lead and the semiconductor chip.
The support tape includes a plurality of electrode pad opening areas and a plurality of bonding part opening areas for exposing the electrode pads of the semiconductor chip and a bonding part of the inner lead to which each of the plurality of the bonding wires are attached. Each electrode pad opening area of the support tape is individually formed to align with each of electrode pads or is formed as one body to align with a row of electrode pads. Also, the support tape may include an active surface opening area partially exposing a portion of the active surface of the semiconductor chip, which is directly contacted to the molding body. Preferably, a bottom surface of the molding body and the bottom surface of the semiconductor chip are aligned, and the bottom surface of the semiconductor chip is exposed from the molding body.
According to another aspect of an embodiment of the present invention, a semiconductor package device is provided which includes a semiconductor chip having an active surface in which a plurality of electrode pads are formed and a bottom surface opposite of the active surface, a plurality of lead frames, each connected to one of the plurality of electrode pads of the semiconductor chip, and each one including a plurality of inner leads having an upper surface, wherein the height of the upper surface is equal to the height of the active surface (i.e., the two surfaces are aligned), a heat-resistant support tape having a plurality of first bonding parts, a plurality of second bonding parts and a routing pattern connecting each first bonding part with an associated second bonding part, attached to the upper surface of the inner lead and the active surface of the semiconductor chip, and supporting the plurality of inner leads and the semiconductor chip. A first bonding wire electrically connects each one of the electrode pads of the semiconductor chip with an associated one of the first bonding parts, and a second bonding wire electrically connects each one of the second bonding parts with an associated one of the inner leads. After the wire bonding is completed, a molding body encapsulates the semiconductor chip, the support tape and the first and second bonding wires.
The support tape further includes an electrode pad opening area and a bonding part opening area for exposing the plurality of electrode pads of the semiconductor chip and a third bonding part of the inner lead to which each first and second bonding wires are attached. Also, the support tape may further include an active surface opening area partially exposing a portion of the active surface of the semiconductor chip, and the exposed portion is directly contacted to and adhering to the molding body. The support tape may be wholly or partially attached to the active surface of the semiconductor chip.
These and other features and aspects of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.
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patent: 5196992 (1993-03-01), Sawaya
patent: 5214845 (1993-06-01), King et al.
patent: 5343074 (1994-08-01), Higgins, III et al.
patent: 5352632 (1994-10-01), Sawaya
patent: 5442231 (1995-08-01), Miyamoto et al.
patent: 5583371 (1996-12-01), Hori
patent: 5585668 (1996-12-01), Burns
patent: 5594626 (1997-01-01), Ros
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
Williams Alexander O.
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