Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-07-08
1999-05-18
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438231, 438586, 438595, 438683, 438785, H01L21/70
Patent
active
059045175
ABSTRACT:
A fabrication process and integrated circuit formed thereby are provided in which relatively thin sidewall spacers extend laterally from opposed sidewall surfaces of a transistor gate conductor. The present invention contemplates forming a gate structure upon a semiconductor substrate. Lightly doped drain impurity areas may be formed in the semiconductor substrate aligned with sidewall of the gate structure. An oxygen-containing dielectric layer is deposited upon the semiconductor topography, followed by deposition of an oxidizable metal upon the dielectric layer. The oxygen-containing dielectric and the oxidizable metal are thermally annealed such that metal oxide spacers are formed adjacent sidewall surfaces of the gate structure. In an embodiment, portions of the dielectric and the metal are selectively removed prior to the anneal. In an alternate embodiment, the metal and the dielectric are annealed first, followed by selective removal of portions of the resulting metal oxide. Following spacer formation, source and drain impurity areas may be formed in the semiconductor substrate aligned with sidewall surfaces of the spacers. A metal silicide may be formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
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patent: 5668024 (1997-09-01), Tsai et al.
patent: 5691225 (1997-11-01), Abiko
patent: 5780362 (1998-07-01), Wang et al.
patent: 5807770 (1998-09-01), Mineji
Fulford Jr. H. Jim
Gardner Mark I.
Wristers Derrick J.
Advanced Micro Devices , Inc.
Chaudhuri Olik
Daffer Kevin L.
Mai Anh D.
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