Ultra high density flash memory

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257314, 257315, 257316, 36518501, 36518526, H01L 2976

Patent

active

059733560

ABSTRACT:
An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F.sup.2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F.sup.2 is needed per bit of data.

REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4604162 (1986-08-01), Sobczak
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4958318 (1990-09-01), Harari
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5017504 (1991-05-01), Nishimuro et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5110752 (1992-05-01), Lu
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5222081 (1993-06-01), Doan
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5376575 (1994-12-01), Kim et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5392245 (1995-02-01), Manning
patent: 5393704 (1995-02-01), Huang et al.
patent: 5396093 (1995-03-01), Lu
patent: 5410169 (1995-04-01), Yamamoto et al.
patent: 5414287 (1995-05-01), Hong
patent: 5422499 (1995-06-01), Manning
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432739 (1995-07-01), Pein
patent: 5438009 (1995-08-01), Yang et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5445986 (1995-08-01), Hirota
patent: 5460316 (1995-10-01), Hefele
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5495441 (1996-02-01), Hong
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508542 (1996-04-01), Geiss et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
patent: 5593912 (1997-01-01), Rajeevakumar
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5644540 (1997-07-01), Manning
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5705415 (1998-01-01), Orlowski et al.
Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM Journal of Research and Development, 39, 167-188, (Jan./Mar. 1995).
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 .mu.m", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Banerjee, S.K., et al., "Characterization of Trench Transistors for 3-D Memories", 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA, 79-80, (May 28-30, 1986).
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625, (Apr. 1992).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613, (1989).
Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 4-7, 1994).
Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", SPIE, 2636, 83-90, (1995).
Chen, M.-J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).
Chen, M.-J., et al., "Optimizing the Match in Weakly Inverted MOSFET's by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung, I.-V., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30--Oct. 3, 1996).
De, V.K., et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Fong, Y., et al., "Oxides Grown on Textured Single-Crystal Silicon--Dependence on Process and Application in EEPROMs", IEEE Transactions on Electron Devices, 37, 583-590, (Mar. 1990).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Bias Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).
Gong, S., et al., "Techniques for Reducing Switching Noise in High Speed Digital Systems", Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, 21-24, (1995).
Hao, M.-Y., et al., "Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon", Appl. Phys. Lett., 60, 445-447, (Jan. 1992).
Harada, M., et al., "Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 96-97, (Jun. 11-13, 1996).
Hisamoto, D., et al., "A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs", 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).
Hodges, D.A., et al., "MOS Decoders", In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, Mc-Graw-Hill Book Co., New York, 354-357, (1988).
Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 .mu.m Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).
Huang, W.L., et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).
Jun, Y.K., et al., "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications", IEEE Electron Device Letters, 13, 430-432, (Aug. 1992).
Kang, H.K., et al., "Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco, CA, 635-638, (Dec. 11-14, 1994).
Kim, Y.-S., et al., "A Study on Pyrolysis DMEAA for Selective Deposition of Aluminum", In: Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, R.C. Ellwanger, et al., (eds.), Materials Research Society, Pittsburgh, PA, 675-680, (1996).
Kishimoto, T.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Ultra high density flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ultra high density flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra high density flash memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-767659

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.