Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-05-15
1999-07-13
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438210, 438230, 438398, 438643, H01L 21336
Patent
active
059239883
ABSTRACT:
A process for fabricating a polycide SAC structure, for a MOSFET device, has been developed. This process features a polycide SAC structure, comprised of tungsten silicide on in situ doped polysilicon, using tungsten hexafluoride and dichlorosilane as reactants for deposition of tungsten silicide. A first thermal anneal treatment is performed prior to polycide patterning, supplying protection to exposed tungsten silicide sides, during the patterning procedure. A second thermal anneal treatment is performed after polycide patterning, and prior to a silicon oxide deposition, offering protection to the exposed top surface of tungsten silicide, during the silicon oxide deposition.
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An Chi-Di
Cheng Kuo-Hsien
Liao Hung-Che
Lin Wen Jan
Sheu Jer-Yuan
Ackerman Stephen B.
Brown Peter Toby
Duong Khanh
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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