Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-23
2001-05-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S199000, C438S649000, C438S652000, C438S655000, C257S369000
Reexamination Certificate
active
06235566
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to optimize source/drain and gate with low resistance, more particularly by using silicide technology to optimize performance of source/drain and gate.
2. Description of the Prior Art
As the time being, integration of integrated circuit, semiconductor device is gradually increased greatly than before. Size of semiconductor device is shorter and shorter than before as well. Therefore, it is important that keeping good operation condition even though the size of semiconductor is measured as small as angstroms. Particularly preferring conventional complementary metal-oxide semiconductor (C.M.O.S.) device, usually used as high-voltage device, is seriously mentioned. Generally the conventional horizontal-direction C.M.O.S. structure will occupy much of space of chip due to it is a widely deposition device. Also, the channel and drift area of conventional C.M.O.S. will occupy horizontal-direction space of chip. Therefore, if possible, it is necessary to be modified geometry of C.M.O.S. device.
Secondly, as the C.M.O.S. channel becomes shorter, the electric field along the channel becomes stronger (for a given power supply voltage). That is, the potential distribution becomes two dimensional, and the effect of the electric field along the channel can no longer be ignored while considering the effects of the electric field normal to the channel.
The conventional art is shown as
FIG. 1A
to FIG.
1
E. From the cross sectional diagram of
FIG. 1A
, substrate
10
, shallow trench isolation
11
, N-well and P-well
12
are all provided.
Then, as
FIG. 1B
, gate oxide
13
is grown up and polysilicon gate
14
is formed by the conventional deposition.
Sequentially, LDD implants can be carried out as source/drain region
15
as FIG.
1
C.
For spacer
16
formation, it is shown as FIG.
1
D. Again, referring with
FIG. 1D
, N+ and P+ well region
15
all will be formed by implanting. Next, source/drain are all annealed as indicated FIG.
1
D.
Finally,
FIG. 1E
shows that sacilide
17
can be formed at the same time on source/drain region
15
and on top surface of polysilicon gate
14
.
As semiconductor device is gradually scaled down, for lower junction leakage of ultra-shallow junction source/drain, thickness in silicide should be reduced. Thus, the scale of silicide on polysilicon gate is also reduced. This will make sheet resistance increase very much in the practical. Therefore, the above problem should be involved in the semiconductor process. It is necessary to widely employ the silicide process for the ultra large semiconductor integrated (ULSI) process.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for optimizing source/drain and polysilicon gate that substantially using a novel silicide process.
The advantages according to the preferred embodiment will be described as the following. There is no source/drain and polysilicon gate bridging due to the wider production window exists. Sheet resistance of polysilicon gate can be suppressed completely. Sheet resistance of source/drain can be optimized for the sub-0.25 um flow in new generation. And, titanium silicide process can be used under sub-0.25 um semiconductor device in new generation.
In the preferred embodiment, firstly, two trench isolation regions are formed in a semiconductor substrate. The isolation regions are separated from each other by an active region. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. A barrier layer is formed on the polysilicon layer. Patterning is carried out to etch portions of the barrier layer. Then the polysilicon layer and the gate oxide layer until the substrate is exposed, thereby forming a gate region substantially located in the midway between the trench isolation regions. The areas between the trench isolation regions and the gate region are respectively used as a source area and a drain area. First ions are implanted into the substrate using the gate region and the trench isolation regions as an implant mask. A dielectric layer is blanket formed over the gate region and the substrate. The dielectric layer is etched back to form dielectric spacer on sidewalls of the gate region. The second ions are implanted into the substrate using the gate region. The dielectric spacer and the trench isolation regions are used as an implant mask. The conductivity type of the first ions are the same as conductivity type of the second ions, and the concentration of the second ions are greater than the concentration of the first ions. The first silicide regions respectively are formed in the source area and the drain area by thermally reacting first metal and the substrate in the source and the drain area. The gate region is prevented from being reacted with the first metal by the protection of the barrier layer and the dielectric spacer. A poly-metal dielectric (PMD) layer is formed over the substrate and the gate region. The poly-metal dielectric layer is etched back and the barrier layer until the surface of the polysilicon layer is exposed. The second silicide region is formed on and in the polysilicon layer by thermally reacting second metal and the polysilicon layer. The source and the drain regions are prevented from further reacting by the protection of the poly-metal dielectric layer.
REFERENCES:
patent: 5130266 (1992-07-01), Huang et al.
patent: 5723893 (1998-03-01), Yu et al.
patent: 5793089 (1999-08-01), Fulford, Jr. et al.
patent: 5933741 (1999-08-01), Tseng
patent: 5943581 (1999-08-01), Lu et al.
patent: 6015746 (2000-01-01), Yeh et al.
patent: 6107131 (2000-08-01), Huang
Lee Granvill
Smith Matthew
United Microelectronics Corp.
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