Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Utility Patent
1998-01-14
2001-01-02
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S654000, C438S688000
Utility Patent
active
06169030
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a metallization process for manufacturing semiconductor devices. More particularly, the present invention relates to the metallization of apertures to form void-free interconnections between conducting layers, including contacts or vias in high aspect ratio, sub-half micron applications.
2. Background of the Related Art
In semiconductor devices, such as integrated circuits, interconnections are used to connect and integrate the various components of the device. Typically, the devices are composed of many layers of conductive components, separated by an insulating material to help minimize signal paths and reduce the size of the device. To establish continuity between the layers, a conductive interconnection (contact or via) extends between the insulating layers and connects the conductive layers. Thus, an interconnection is a vertical opening filled with conductive material used to connect components on various layers of a device to one another and to the semiconducting substrate.
As the integration of semiconductor devices increases, the sizes of interconnections has been reduced and their aspect ratios (i.e., the ratio of the height of the interconnection to the width) has increased. As a result, methods that in the past were sufficient to fill the interconnections have proved insufficient for the smaller interconnections. Typically, interconnection apertures are filled using a metal material, such as tungsten, aluminum and more recently copper, that is deposited inside the apertures by chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or a combination thereof. A primary problem associated with the filling of small interconnections is that voids tend to form within the interconnections.
A void is an enclosed area devoid of deposited material that is typically formed when two adjoining cusps over step corners of an aperture meet across the space adjoining the vertical feature to form a “bridge.” Because sputtered atoms (in PVD) typically follow “line-of-sight” trajectories, a shadowing effect occurs at the aperture and leads to a thinner growth of the metal deposited within the aperture and an accelerated growth rate at the upper step corners of the aperture. The build-up of material at the upper step corners of the aperture creates overhangs or cusps at the corner. If the cusps join before the interior of the aperture is filled, the cusps form a bridge and seal the top of the aperture, thereby creating a void. This effect is generally referred to as “bridging.”
FIG. 1
is a cross sectional side view of an interconnection illustrating the formation of cusps at the upper step corners of the aperture.
FIG. 2
is a cross sectional side view of an interconnection illustrating bridging and the formation of a void in the interconnection.
A void formed in an interconnection may result in a defective circuit and, thus, a defective device. For example, when current passes through the interconnection, the thin internal layers of material adjacent the void in the interconnection may increase the resistance and current density in the thin area which results in a break or open circuit in the interconnection. Consequently, the device fails because of a defective interconnection. Therefore, complete filling of the apertures and the avoidance of voids is critical to ensure reliability of the device.
One method of overcoming void formations uses substrate bias sputtering to re-sputter materials deposited on the side walls of the aperture down to the bottom of the aperture. However, substrate bias sputtering utilizes high re-sputtering rates which reduce the net rate of deposition. Additionally, heavy re-sputtering can cause significant argon incorporation in the films which is known to increase electromigration resistance.
Another attempt to overcome void formations uses CVD to deposit thin conformal layer of aluminum (Al) in high aspect ratio contacts and vias at low temperatures. However, transmission electron microscopy (TEM) data has revealed that continued CVD deposition to complete filling of the interconnection typically still causes bridging and results in the formation of voids.
Another technique for metallization of high aspect ratio apertures is hot planarization PVD which deposits a thin layer of refractory material, such as titanium (Ti), on a patterned wafer to form a wetting layer onto which either (1) a hot PVD Al layer is deposited or (2) a warm PVD Al layer is deposited followed by a hot PVD Al layer. However, hot PVD Al processes are very sensitive to the quality of the wetting layer, wafer condition, and other processing parameters. Small variations in processing conditions or poor coverage of the PVD Ti wetting layer can result in incomplete filling of the apertures, thus creating voids. Thus, even at high temperatures, hot PVD Al processes may still result in bridging and void formation. Furthermore, in order to reliably fill vias and contacts, hot PVD Al processes must be performed at temperatures above about 450° C. which may damage certain components of the device.
Interconnection filling processes that use a CVD process followed by a PVD process have evolved as the most effective manner of interconnection formation for sub-half micron interconnections having an aspect ratio greater than one. Typically, a thin, conformal layer of CVD metal, such as Al, is deposited as a wetting layer to partially fill the aperture, followed by a PVD metal film, such as AlCu, which completely fills the aperture to form the interconnect. This CVD/PVD process has been used successfully for metallization of interconnection structures having sub-half micron apertures with aspect ratios of 5:1.
However, even when using the CVD/PVD process, as the size of the interconnections are reduced, the surface diffusion of the metal into the apertures stops and the hole filling process is then controlled by the solid phase, or bulk diffusion, which is a highly thermally active process. Therefore, achieving interconnection fill using the CVD/PVD process requires a large thermal budget. Accordingly, the PVD metal must be deposited at a low plasma power of less than two kilowatts for a 200 mm substrate, and the low power plasma is typically kept constant throughout the deposition process. However, the low power PVD metal deposition provides unacceptably low reflectivity and a rough, non-planarized morphology of the integrated CVD/PVD stack. Furthermore, using a low power plasma increases the time required to fill the interconnections, and thus, the processing time in the chamber. The increased time in the chamber decreases the throughput of the system.
In addition to overcoming void formation within the interconnection, the metallization process also needs to produce surfaces having high reflectivity. Reflectivity is a measure of the surface roughness, or smoothness, as determined by the amount of light reflected from the surface. Rougher surfaces are less reflective while smooth surfaces are more reflective. Typically, the reflectivity is expressed as a percentage of a known standard surface such as bare silicon which is defined as having a reflectivity of one hundred percent. A reflectivity greater than about 170 percent is desirable to provide successful process integration with subsequent photolithography and metal etch.
FIG. 3
illustrates a cross section of a semiconductor substrate contact deposited using low power plasma PVD. The 0.35 micron contact having an aspect ratio of 3:1 was produced using a low power plasma of about 1 kW (over a 200 mm substrate) in a single-step PVD AlCu process at 400° C. Although the process did not produce any voids, the surface morphology is very rough, and the reflectivity is about 60 percent. Furthermore, the time required to complete the deposition was about 233 seconds. Thus, deposition using low power plasma (less than about five kilowatts for a 200 mm substrate) results in an unsatisfactory film reflectivity of less than about sixty percent
Beinglass Israel
Chen Liang-Yuh
Guo Ted
Mosely Roderick Craig
Naik Mehul B.
Applied Materials Inc.
Everhart Caridad
Thomason Moser & Patterson
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