Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2007-07-31
2007-07-31
Norton, Nadine (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S692000, C438S694000, C438S690000, C438S689000, C438S700000, C438S740000, C216S017000, C216S018000, C216S039000, C216S041000, C216S058000, C257S758000, C257S759000, C257S760000
Reexamination Certificate
active
10666354
ABSTRACT:
A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of H2O or CH4during the He treatment. The low k dielectric layer is then treated with a H2plasma which converts some of the Si—O and Si—CH3bonds near the surface to Si—H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two H2treatment are performed.
REFERENCES:
patent: 6028015 (2000-02-01), Wang et al.
patent: 6103601 (2000-08-01), Lee et al.
patent: 6147009 (2000-11-01), Grill et al.
patent: 6204204 (2001-03-01), Paranjpe et al.
patent: 6346488 (2002-02-01), Kabansky
patent: 6372301 (2002-04-01), Narasimhan et al.
patent: 6403464 (2002-06-01), Chang
patent: 6436808 (2002-08-01), Ngo et al.
patent: 6465372 (2002-10-01), Xia et al.
patent: 6528423 (2003-03-01), Catabay et al.
patent: 6936533 (2005-08-01), Kim et al.
S. Wolf, Silicon Processing for the VLSI Era, vol. 1, p. 441, Lattice Press, (1986).
Patent Application TSMC-02-520, U.S. Appl. No. 10/421,187, filed Apr. 23, 2003, assigned to a common assignee, “Solution for FSG Induced Metal Corrosion & Metal Peeling Defects with Extra Bias Liner and Smooth RF Bias Ramp Up,” discusses an integrated circuit device.
Bao Tien I.
Chang Hui-Lin
Ko Chung-Chi
Lu Yun-Chen
Angadi Maki
Haynes and Boone LLP
Norton Nadine
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Two step post-deposition treatment of ILD layer for a lower... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two step post-deposition treatment of ILD layer for a lower..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two step post-deposition treatment of ILD layer for a lower... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3792240