Twin cell architecture for integrated circuit dynamic random...

Details Twin cell architecture for integrated circuit dynamic random... Twin cell architecture for integrated circuit dynamic random...

2011-03-29

2011-03-29

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S230060

Reexamination Certificate

active

07916567

ABSTRACT:
A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.

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