Trench isolation methods including plasma chemical vapor deposit

Details Trench isolation methods including plasma chemical vapor deposit Trench isolation methods including plasma chemical vapor deposit

1998-03-31

1999-12-14

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438404, 438405, 438424, 438400, H01L 2176, H01L 21336

Patent

active

060016965

ABSTRACT:
Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region. Isolation trenches so formed can have improved isolation characteristics and can be planarized with reduced dishing effects.

REFERENCES:
patent: 4599136 (1986-07-01), Araps et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5923993 (1999-07-01), Sahota
Notice of Office Action, Korean Applicatiion No. 97-20989, Jun. 28, 1999.

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