Transistor with local insulator structure

Details Transistor with local insulator structure Transistor with local insulator structure

2000-05-24

2003-12-30

Clark, Sheila V. (Department: 2815)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S297000, C438S225000, C257S327000, C257S647000, C257S351000

Reexamination Certificate

active

06670260

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to integrated circuit (IC) devices and processes for making IC devices. More particularly, the present invention relates to an IC which includes transistors with a local buried insulator.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.
In bulk semiconductor-type devices, transistors, such as, MOSFETs are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of the depletion layer below the inversion channel) must be scaled down to achieve superior short channel performance.
According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing). The ion implantation process can generally only achieve a 80 nanometer or larger body thickness for a transistor. Thus, conventional fabrication techniques for bulk semiconductor type-devices cannot create transistors with body thickness less than 80 nm.
Accordingly, bulk semiconductor-type devices can be subject to disadvantageous properties due to the relatively large body thicknesses. These disadvantageous properties include less than ideal sub-threshold voltage rolloff, short channel effects, and drain induced barrier layering. Further still, bulk semiconductor-type devices can be subject to further disadvantageous properties such as high junction capacitance, ineffective isolation, and low saturation current. These properties are accentuated as transistors become smaller and transistor density increases on ICs.
Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate. The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current. As transistors become smaller, the thin film semiconductor substrate also becomes thinner. The thinness of the thin film semiconductor substrate prevents effective silicidation on the thin film semiconductor substrate. Effective silicidation is necessary to form source and drain contacts. Without effective silicidation, the transistor can have large source/drain series resistances.
Typically, silicidation must consume a certain volume of the semiconductor substrate (e.g., silicon), which is not abundantly available on the thin film semiconductor substrate. The significant volume of the substrate must be consumed to appropriately make electrical contact to the source and drain regions. Accordingly, SOI-type devices are susceptible to the high series resistance which can degrade transistor saturation current and hence, the speed of the transistor. The high series resistance associated with conventional SOI CMOS technology is a major obstacle which prevents SOI technology from becoming a mainstream IC technology.
Thus, there is a need for a thin-film, fully depleted MOSFET IC which has advantages over conventional bulk type devices. Further still, there is a need for a transistor which has superior short-channel performance, near ideal subthreshold swing, and high saturation current and yet is not susceptible to high series resistance. Even further still, there is a need for a thin film transistor which has sufficient silicon for effective silicidation.
SUMMARY OF THE INVENTION
The present invention relates to an integrated circuit including a first wafer layer and a second wafer layer. The first wafer layer includes a plurality of insulator regions disposed on a first semiconductor substrate. The second wafer layer is disposed above the first wafer layer and includes a plurality of transistors disposed in a second semiconductor substrate. Each of the transistors includes a gate disposed between a source region and a drain region. Each of the transistors is disposed above a respective insulator region of the insulator regions.
The present invention further relates to an ultra-large scale integrated (ULSI) circuit including a plurality of field effect transistors. The transistors include a gate disposed above a channel region. The channel region is between a source region and a drain region. The channel region is located on a first substrate above a local insulator means for reducing transient enhanced diffusion on a second substrate.
The present invention even further still relates to a ULSI circuit including a plurality of transistors. Each transistor has a local insulator region. The integrated circuit is manufactured by steps including forming a plurality of insulator regions on a top surface of a first semiconductor substrate, attaching a bottom surface of a second semiconductor substrate to the top surface, and forming a plurality of gate structures on the second semiconductor substrate. The gate structures are located above respective insulator regions of the regions.


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