Transistor with dopant-bearing metal in source and drain

Details Transistor with dopant-bearing metal in source and drain Transistor with dopant-bearing metal in source and drain

2005-07-26

2005-07-26

Tran, Thien F (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S369000, C438S542000

Reexamination Certificate

active

06921691

ABSTRACT:
A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.

REFERENCES:
patent: 5162263 (1992-11-01), Kunishima et al.
Gannavaram, S. et al., “Low Temperature (≦ 800° C) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70 nm CMOS,” 0-7803-6441-4/00, IEEE/North Carolina State University, Raleigh, NC, 2000.
Huang, F.J., et al., “Schottky-Clamped NMOS Transistors Implemented in a Conventional 0.8-μm CMOS Process,” IEEE Electron Device Letters, Sep., 1998, pp. 326-328, vol. 19, No. 9, IEEE, New York, NY.
“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2002 Update, pp. 45-62, http://member.itrs.net/.
“Front End Processes,” International Technology Roadmap for Semiconductor (ITRS), 2003 Edition, pp. 23-25, http://member.itrs.net/.

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