Transistor structure with dual trench for optimized stress...

Details Transistor structure with dual trench for optimized stress... Transistor structure with dual trench for optimized stress...

2007-10-02

2007-10-02

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S218000, C257SE21546

Reexamination Certificate

active

10977266

ABSTRACT:
A method for forming a portion of a semiconductor device structure comprises providing a semiconductor-on-insulator substrate having a semiconductor active layer, an insulation layer, and a semiconductor substrate. A first isolation trench is formed within the semiconductor active layer and a stressor material is deposited on a bottom of the first trench, wherein the stressor material includes a dual-use film. A second isolation trench is formed within the semiconductor active layer, wherein the second isolation trench is absent of the stressor material on a bottom of the second trench. The presence and absence of stressor material in the first and second isolation trenches, respectively, provides differential stress: (i) on one or more of N-type or P-type devices of the semiconductor device structure, (ii) for one or more of width direction or channel direction orientations, and (iii) to customize stress benefits of one or more of a <100> or <110> semiconductor-on-insulator substrate.

REFERENCES:
patent: 6174784 (2001-01-01), Forbes
patent: 6482715 (2002-11-01), Park et al.
patent: 6524929 (2003-02-01), Xiang et al.
International Search Report and Written Opinion.

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