Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-09
2003-10-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S264000
Reexamination Certificate
active
06632717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a dual gate electrode having a stacked structure comprising a first gate electrode and a second gate electrode larger than the first gate electrode.
2. Description of the Background Art
Conventional semiconductor devices have problems, such as RC delay, short channel effects, and increased contact resistance as junction depth is decreased.
As a result, a salicide structure, an elevated source/drain (“ESD”), or both are employed to form a source/drain region on a semiconductor substrate, such as by a selective epitaxial process.
FIGS. 1
a
through
1
d
illustrate a conventional method of fabricating a transistor. A gate oxide
13
and a gate electrode
15
are formed on a p-type semiconductor substrate
11
(see
FIG. 1
a
). A lightly doped drain region (hereinafter referred to as the ‘LDD’ region)
17
is then formed by ion-implanting low concentration, low energy n-type impurities and using a mask on the surface of the semiconductor substrate
11
at both sides of the gate electrode
15
(see
FIG. 1
b
). Next, an oxide film is formed on the entire surface including the gate electrode
15
. The oxide film is etched to form an oxide spacer
19
on side walls of the gate electrode
15
(see
FIG. 1
c
). A source/drain region
21
is formed on the exposed region of the semiconductor substrate
11
by ion-implanting high concentration, high energy n-type impurities using the oxide spacer
19
and the gate electrode
15
as masks (see
FIG. 1
d
).
However, the conventional method of fabricating a transistor has several problems. The width of a gate electrode is limited by the thickness of the polysilicon layer, which is used to form the gate electrode, and the etching selectivity of the photoresist layer used as a mask for etching the polysilicon layer.
It is difficult to decrease the width of the photoresist layer. The thickness of the photoresist layer must often be maintained at a certain level. In addition, a limit in the channel length can also prevent high integration.
In addition, when the width of the gate electrode is reduced, the surface resistance of the gate electrode increases and, thus, deteriorates the performance characteristics of the device. Furthermore, when a contact hole is formed at the upper side of the gate electrode, the process margin of the contact hole decreases and, thereby, potentially allowing a short circuit between the gate electrode and the active region, and resulting in decreased yield and reliability of the device.
SUMMARY OF THE INVENTION
In accordance with the present invention, a transistor of a semiconductor device comprises: a gate insulating film formed on a semiconductor substrate; a first gate electrode formed on the gate insulating film; a lightly doped drain (LDD) region formed on the semiconductor substrate at both sides of the first gate electrode; an oxide pattern of a predetermined width formed at a side wall of the first gate electrode; a second gate electrode formed at an upper portion of the first gate electrode and the oxide pattern; and a source/drain region formed on the semiconductor substrate at both sides of the second gate electrode.
In accordance with another aspect of the present invention, a method of fabricating a transistor of a semiconductor device comprises: sequentially forming a gate insulating film on a semiconductor substrate and a first gate electrode on the gate insulating film; forming a lightly doped drain (LDD) region on the semiconductor substrate at both sides of the first gate electrode; forming an insulating film; forming a groove exposing an upper portion of the first gate electrode by removing a portion of the insulating film at an upper portion of the first gate electrode, wherein a width of the removed portion of the insulating film is larger than that of the first gate electrode; forming a second gate electrode contacting the first gate electrode by filling the groove; forming an insulating film pattern at both sides of the first gate electrode by removing the insulating film at both sides of the second gate electrode and to expose the semiconductor substrate; and forming a source/drain region on the semiconductor substrate at both sides of the second gate electrode.
Additional features of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 6207007 (2001-03-01), Segawa et al.
patent: 6309933 (2001-10-01), Li et al.
patent: 6426529 (2002-07-01), Kobayashi
patent: 6429072 (2002-08-01), Tsukiji
Kim Jong Il
Kim Kil Ho
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hynix / Semiconductor Inc.
Lindsay Jr. Walter L.
Niebling John F.
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