Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-12
2001-10-23
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S394000, C257S547000, C438S300000
Reexamination Certificate
active
06307230
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices, and more particularly to a transistor having an improved sidewall gate structure and method of construction.
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are constructed from various microelectronic devices, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is generally constructed from a pattern of conductor, semiconductor, and insulator regions that are formed on a semiconductor substrate.
A Field Effect Transistor (FET) generally includes a conductive gate formed near the semiconductor substrate to control the flow of current from a source to a drain of the transistor. One type of FET utilizes a raised source and drain to increase the amount of current that can be switched by the transistor. A sidewall insulation body formed between the gate and the raised source and drain is used to prevent the gate from shorting to the raised source and drain. The gate in combination with the sidewall insulation body and the raised drain generally forms an unwanted parasitic capacitance, often referred to in the art as a gate-to-drain capacitance.
As the geometries of microelectronic devices decrease and the density of the microelectronic devices in a semiconductor component increase, the distance between the gate and the drain of the transistor decreases, resulting in a corresponding increase in the gate-to-drain capacitance. The higher the gate-to-drain capacitance, the greater the adverse affect on the operation of the transistor. For example, the higher the gate-to-drain capacitance, the slower the switching speed of the transistor.
In addition, some gate fabrication techniques utilize an etching process, such as plasma etching or wet chemical etching, to chemically remove material to form the microelectronic devices. Some etching processes used in fabricating the gate removes material that would otherwise be beneficial to the construction or operation of the microelectronic device. The loss of the beneficial material during the etching process can reduce the manufacturability or operating ability of the gate, transistor, semiconductor component, and the electronic equipment.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for a transistor having an improved sidewall gate structure and method of construction. The present invention provides a transistor having an improved sidewall gate structure and method of construction that substantially eliminates or reduces problems associated with the prior devices and methods.
In accordance with one embodiment of the present invention, a method of forming a sidewall gate structure comprises forming a primary insulation layer adjacent a substrate. The substrate includes a first and second doped region separated by a channel region. A disposable gate is formed adjacent to the primary insulation layer proximate the channel region of the substrate. A sidewall insulation body is then formed adjacent to the disposable gate. The sidewall insulation body is comprised of a silicon oxynitride (oxynitride) material. The primary insulation layer proximate the first and second doped regions is removed to expose a portion of the substrate. An epitaxial layer is formed on the exposed portion of the substrate and a buffer layer is then formed outwardly from the epitaxial layer. The disposable gate is removed to expose a portion of the primary insulation layer proximate the channel region of the substrate. The exposed portion of the primary insulation layer is removed to expose the channel region of the substrate. The sidewall insulator body is not etched substantially by the same etch process that etches the primary insulation layer. A gate insulator is formed on the exposed channel portion of the substrate. A gate is then formed adjacent the gate insulator.
Important technical advantages of the present invention include providing an improved gate structure having a sidewall insulating body formed from an oxynitride material. The oxynitride material has the technical advantage of having a lower dielectric constant than many conventional materials used in sidewall insulation bodies. Accordingly, the gate-to-drain parasitic capacitance of the transistor may be reduced and the transistor can switch at a higher speed.
Another technical advantage of the present invention is that the buffer layer is not substantially removed during subsequent etching processes. Accordingly, the transistor may have an increased resistance to charge leakage and shorting between the gate and the source or drain.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 5118639 (1992-06-01), Roth et al.
patent: 5168072 (1992-12-01), Moslehi
patent: 5252501 (1993-10-01), Moslehi
patent: 5824587 (1998-10-01), Krivokapic
patent: 5902125 (1999-05-01), Wu
patent: 6160299 (2000-12-01), Rodder
Ali Iqbal
Chatterjee Amitava
Hames Greg A.
Hanratty Maureen A.
He Quzhi
Brady III W. James
Jr. Carl Whitehead
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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