Tiny ball grid array package

Details Tiny ball grid array package Tiny ball grid array package

1999-08-26

2001-04-17

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S678000, C257S684000, C257S687000, C257S693000, C257S698000, C257S701000, C257S707000, C257S777000, C257S778000, C257S779000, C257S780000, C257S781000, C257S782000, C257S783000, C257S784000

Reexamination Certificate

active

06218731

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88108359, filed May 21, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a tiny ball grid array package, and more particularly, to a tiny ball grid array package with an improved thermal and electrical performance.
2. Description of the Related Art
In an integrated circuit, signal lines formed upon the silicon substrate to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. The integrated circuit is then secured within a protective semiconductor device package. Each of the I/O pads of the chip is then connected to one or more terminals of a device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip of the terminals of the device package. Some types of device packages have terminals called pins for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a PCB.
As the semiconductor technique has been updated with an increasingly higher integration and speed, the fabrication technique with a linewidth of about 0.18 micron has been achieved in mass production. The objective of being “compact, thin and light”, has been a leading trend for the development of various aspects of semiconductor fabrication, including package technique. In addition, in view of operating an electronic device with increasingly higher operating speed, how to comply with the effect caused by the improved high frequency in package and how to improve heat dissipation are important topics in factory, as well.
FIG. 1
shows a schematic, cross-sectional structure of a conventional lead on chip package. The lead on chip package is commonly applied in a thin small outline package (TSOP). The lead on chip package uses a lead frame
24
, which has a different structure from normal lead frames. The lead frame
24
comprises only multiple leads
10
. A chip
12
has a surface
14
comprising bonding pads
16
which surface
14
is directly adhered onto the leads
10
using, for example, a double adhesive polyimide tape
18
. The bonding pads
16
are disposed in positions on the surface
14
and near central portion of the surface
14
. Each bonding pad
16
is coupled to one conductive wire
20
and a lead
10
. A package material
22
encloses the chip
12
, the conductive wire
20
, and the connecting regions between leads
10
and bonding pads
16
. In the lead on chip package structure, the usage of die pad is saved to result in a reduced package area and volume. By directly adhering the chip to the leads, a better heat dissipation path is provided. However, due to restriction imposed by a pitch inherent to the lead frame, it is difficult to effectively reduce the package size for high pin count devices. It is also difficult to resolve the high frequency inductance effect.
FIG. 2
shows a schematic, cross-sectional view of another conventional lead on chip package. The package structure shown in
FIG. 2
is also called a tiny ball grid array or a thin and fine ball grid array. A ball grid array substrate is used as a carrier. A single layer of a ball grid array substrate
34
laminated with an inner layer of resin
30
and a copper foil
32
is used in the conventional structure. The inner layer
30
has an aperture
42
near a center thereof. The copper foil
32
is disposed on a surface
40
of the inner layer
30
, and patterned into conductive traces
31
. A surface
14
comprising bonding pads
16
of the chip
12
is adhered onto another surface
38
of the inner layer
30
using adhesive
44
. The bonding pads
16
are formed on the chip
12
near a center thereof. When the chip
12
and the inner layer
30
are adhered to each other, the bonding pads
16
are aligned with the aperture
42
. When a bonding process is performed to connect the bonding pads
16
and a near end
31
a
of the conductive trace
31
with bonding wires
20
going through the aperture
42
. The connection of the bonding wires
20
and the conductive trace
31
a
is then sealed in a package material
22
to protect the adhering parts of the chip
12
and the ball grid array substrate
34
. A far end
31
b
of the conductive trace
31
has another terminal having solder balls
36
disposed thereon to provide a connection to an external circuit, for example, such as a terminal for transferring a signal to a printed circuit board.
The above lead on chip package structure uses a ball grid array substrate instead of a conventional lead frame to reduce the pitch and size. However, heat is mainly generated from a surface comprising semiconductor devices which is taped with an inner layer, so that the effect heat dissipation is poor and degrades the performance of products. To effectively resolve the problems of heat dissipation, a heat sink is required on the chip to increase the cost of products. On the other hand, since the pitch between wires is smaller, the inductance effect is more obvious for a high frequency operation. The interference of signal becomes more serious and degrades the performance of products.
SUMMARY OF THE INVENTION
The invention provides a tiny ball grid array package in which a chip is directly adhered onto a copper layer, so that the heat dissipation efficiency is improved.
In the tiny ball grid array package provided by the invention, a ground plane is formed to reduce the signal transmission path and suppress the occurrence of a signal noise. Mutual induction can also be reduced to shorten the signal delay time.
The invention provides a tiny ball grid array package structure on a substrate comprising at least an insulation layer and two copper layers laminated on each surface of the insulation layer. The substrate has a central hollow portion. A second copper layer of these two copper layers is patterned into multiple conductive traces and disposed on a surface of the substrate. A surface of the first copper layer is partially exposed and electrically connected to the conductive traces by vias, so as to be grounded to form a ground plane. The chip has a surface comprising bonding pads near the central hollow. The surface of the chip is thermal-conductively connected with the ground plane. The bonding pads are located within the hollow portion. The bonding pads are electrically connected to a near end of the conductive traces by a conductive wire, while a far end of the conductive traces is implanted with solder balls. The hollow portion and an area surrounding the hollow portion is filled with a molding material to protect the bonding pads, the conductive wire and the conductive traces, and does so by covering a junction area of the chip and the ground plane.
According to the invention, the substrate comprises a dual layer plate. Two copper layers are laminated onto two surfaces of an insulation layer, respectively. When a lamination of more than three copper layers is used, a ground plane is preferably disposed on other coppers layers. The first copper layer is connected to ground to form a ground plane. Thus, the signal transmission path can be reduced with a reduced mutual inductance. Under a high operation frequency, the inductance effect and signal delay can be improved. In addition, by directly connecting the chip with the ground plane, an enhanced heat dissipation path is provided.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5677575 (1997-10-01), Maeta et al.
patent: 5731709 (1998-03-01), Pastore et al.

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