Timing closure for system on a chip using voltage drop based...

Details Timing closure for system on a chip using voltage drop based... Timing closure for system on a chip using voltage drop based...

2008-01-29

2008-01-29

Nghiem, Michael (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

C716S030000

Reexamination Certificate

active

07324914

ABSTRACT:
A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.

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