Static information storage and retrieval – Systems using particular element – Resistive
Reexamination Certificate
2011-08-09
2011-08-09
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Systems using particular element
Resistive
C365S175000
Reexamination Certificate
active
07995371
ABSTRACT:
A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
REFERENCES:
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6518156 (2003-02-01), Chen et al.
patent: 6534784 (2003-03-01), Eliasson et al.
patent: 6545898 (2003-04-01), Scheuerlein
patent: 6563185 (2003-05-01), Moddel et al.
patent: 6741495 (2004-05-01), Kunikiyo et al.
patent: 6756649 (2004-06-01), Moddel et al.
patent: 6762071 (2004-07-01), Eliasson et al.
patent: 6972238 (2005-12-01), Hsu et al.
patent: 7060586 (2006-06-01), Li et al.
patent: 7105852 (2006-09-01), Moddel et al.
patent: 7148533 (2006-12-01), Hsu et al.
patent: 7173275 (2007-02-01), Estes et al.
patent: 7218984 (2007-05-01), Bayat et al.
patent: 7256429 (2007-08-01), Hsu et al.
patent: 7388276 (2008-06-01), Estes et al.
patent: 7408212 (2008-08-01), Luan et al.
patent: 7417271 (2008-08-01), Genrikh et al.
patent: 7446010 (2008-11-01), Li et al.
patent: 7459716 (2008-12-01), Toda et al.
patent: 7460385 (2008-12-01), Gruber et al.
patent: 7462857 (2008-12-01), Arai et al.
patent: 7558099 (2009-07-01), Morimoto
patent: 7569459 (2009-08-01), Karg et al.
patent: 7577022 (2009-08-01), Muraoka et al.
patent: 7606086 (2009-10-01), Inoue
patent: 7633108 (2009-12-01), Li et al.
patent: 2002/0114112 (2002-08-01), Nakashio et al.
patent: 2003/0151959 (2003-08-01), Tringali et al.
patent: 2004/0100817 (2004-05-01), Subramanian et al.
patent: 2004/0114413 (2004-06-01), Parkinson et al.
patent: 2004/0161888 (2004-08-01), Rinerson et al.
patent: 2005/0083760 (2005-04-01), Subramanian et al.
patent: 2005/0111263 (2005-05-01), Rinerson et al.
patent: 2006/0273301 (2006-12-01), Moddel et al.
patent: 2007/0120110 (2007-05-01), Estes et al.
patent: 2008/0173975 (2008-07-01), Chen et al.
patent: 2008/0272363 (2008-11-01), Mouli
patent: 2008/0273363 (2008-11-01), Mouli
patent: 2009/0026434 (2009-01-01), Malhotra et al.
Caperson, J. D.; Atwater, H. A.; Bell, L. D., “Layered Tunnel Barriers for Silicon Based Nonvolatile Memory Applications”, Power Point Slides, Caltech, May 17, 2004, pp. 1-16.
Caperson, J. D., “Design and Characterization of Layered Tunnel Barriers for Nonvolatile Memory Applications”, PhD Thesis, Caltech, May 17, 2004, pp. 1-143.
Caperson, J. D.; Atwater, H. A.; Bell, L. D., “Materials Issues for Layered Tunnel Barrier Structures”, J. Appl. Phys., vol. 92, No. 1, Jul. 1, 2002, pp. 261-267.
Caperson, J. D.; Atwater, H. A.; Bell, L. D., “Determination of Energy Barrier Profiles for High-K . . . ”, Appl. Phys. Lett., vol. 85, No. 18, Nov. 1, 2004, pp. 4133-4135.
Peacock, P. W.; Robertson, J., “Band Offsets and Schottky Barrier Heights of High Dielectric Constant Oxides”, J. Appl. Phys., vol. 92, No. 8, Oct. 15, 2002, pp. 4712-4721.
Korotkov, A; Likharev, K., “Resonant Fowler-Nordheim Tunneling Through Layered Tunnel Barriers and its Possible Applications”, Techn. Dig. IDEM 1999, pp. 223-226.
Likharev, K. K., “Layered Tunnel Barriers for Nonvolatile Memory Devices”, Appl. Phys., vol. 73, No. 15, Oct. 12, 1998, pp. 2137-2139.
Mikolajick, T. et al., “Scaling of Nonvolatile Memories to Nanoscale Sizes”, Mat Sci—Poland, vol. 25, No. 1, 2007, pp. 33-43.
Tans, S. J.; Verschueren, A. R. M.; Dekker, C., “Room-Temperature Transistor Based on a Single Carbon Nanotube”, Nature, vol. 393, May 7, 1998, pp. 49-52.
Luryi, S.; Kazarinov, R. F., “Optimum Baritt Structure”, Solid-State Electron., vol. 25, No. 9, 1982, pp. 943-945.
Brewer Julie Casperson
Chevallier Christophe J.
Kinney Wayne
Lambertson Roy
Rinerson Darrell
King Douglas
Nguyen Vanthu
Unity Semiconductor Corporation
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