Three-layer lower capacitor electrode

Details Three-layer lower capacitor electrode Three-layer lower capacitor electrode

2007-08-14

2007-08-14

Dickey, Thomas L. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S298000

Reexamination Certificate

active

08820374

ABSTRACT:
A method for forming the lower electrode of a capacitor used for fabricating a 1-Gbit or above DRAM, using a material having a high dielectric constant, is used in a method for manufacturing a storage capacitor of a VLSI semiconductor device. The lower electrode, which is to be in contact with a high dielectric film, is formed to have a triple-structured storage node pattern. The lowest layer of the lower electrode is formed with TiN which serves as a barrier against the diffusion of impurities from a lower substrate. The middle layer of the lower electrode is formed with RuO2which is easy to pattern. The uppermost layer of the lower electrode is formed with Pt which has excellent leakage current properties.

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