Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-01-06
2001-01-16
Chang, Joni (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S268000
Reexamination Certificate
active
06174763
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to integrated semiconductor circuits formed as part of trench structures, and more particularly, to vertical transistors and memory cells disposed completely within a semiconductor trench structure and to associated fabrication methods therefor.
BACKGROUND OF THE INVENTION
As the integrated circuit industry continues to explore techniques used to pack more circuits into a given semiconductor substrate, more and more thought is devoted to not only orienting the various devices in planar fashion along the surface of the substrate, but also to orienting the devices vertically. Typically, this is performed by either building up from the substrate surface or by burying devices in trenches formed within the face of the semiconductor body.
Parallel with an exponential growth in the use of integrated circuit (“IC”) chips has been the development of numerous types of semiconductor memory devices. Advancements in semiconductor technology have made possible memory chips with millions of locations for storing bits of data information. While each generation of memory chips continues to quadruple the number of available storage locations, the size of the integrated circuit chip must yet be maintained within certain limits to enhance production yields and accommodate conventional packaging schemes.
One common memory cell employed in large integrated circuit memory chips comprises a static random access memory (“SRAM”) cell wherein a bit is represented by the state of a circuit comprising a pair of cross-coupled inverters. A majority of SRAMs are fabricated using field effect transistor (“FET”) technology. With appropriate voltage adjustment, these circuits can be reduced in area simply by scaling to a smaller dimension. Specifically, all dimensions of the various process masks can be uniformly shrunk so that the resulting circuitry is fabricated in a smaller area on the wafer. One obvious limitation of scaling an integrated circuit is the photolithographic technique used to form and maintain registration of the various masks. Thus, other methods for reducing the size of individual SRAM “cells” so as to increase the memory density on an IC chip are necessary.
Many different types of semiconductor trench constructions have been proposed in the art, all aimed at reducing the cell size of SRAMs and other circuit components without compromising the performance of the circuit. One approach taken in the art to conserve semiconductor wafer area is to form the transistors comprising the SRAM cell in a vertical orientation in a trench rather than in a lateral orientation across the surface of the substrate. However, as of this date, no complete SRAM cell has been formed in association with a single trench. Thus, a need exists for additional trench structures, particularly new multiple device trench structures which facilitate the fabrication of extremely high density IC chips
DISCLOSURE OF THE INVENTION
Briefly described, in a first aspect, the present invention comprises a semiconductor trench structure. The semiconductor trench structure includes a substrate, a first semiconductor device disposed on the substrate and a second semiconductor device disposed substantially adjacent to the first semiconductor device. Further, a trench intersects the first semiconductor device and the second semiconductor device. Disposed within the trench is means for electrical connection which is electrically connected to the first semiconductor device and the second semiconductor device such that they are electrically cross-coupled within the trench. A semiconductor device may comprise, for example, a field-effect transistor (“FET”).
As an enhancement, the semiconductor trench structure may also include a third semiconductor device and a fourth semiconductor device, each being intersected by the trench. The means for electrical connection may comprise coaxial wiring which may electrically cross-couple the third and fourth semiconductor devices as well as the first and second semiconductor devices.
Further enhancements may comprise locating the first and second semiconductor devices at a first sidewall of the trench, while the third and fourth semiconductor devices may be located at a second sidewall of the trench. Moreover, the second semiconductor device may be located above the first semiconductor device and the fourth semiconductor device may be located above the third semiconductor device.
In another aspect, the present invention comprises a method for forming a semiconductor trench structure. The method includes the steps of providing a substrate, forming a first semiconductor device on the substrate and forming a second semiconductor device substantially adjacent to the first semiconductor device. A trench is then formed intersecting the first and second semiconductor devices. Furthermore, the method includes electrically cross-coupling the first and second semiconductor devices within the trench.
As an enhancement, the method may include forming a third semiconductor device coplanar with the first semiconductor device and forming a fourth semiconductor device coplanar with the second semiconductor device. The electrical cross-coupling may then be performed such that the third and fourth semiconductor devices are also electrically crosscoupled within the trench.
As further enhancements, the steps of forming the first and third semiconductor devices may comprise forming a first silicon-on-insulator (“SOI”) layer on the substrate, and forming the first and third semiconductor devices within a silicon layer thereof. Similarly, the steps of forming the second and fourth semiconductor device may comprise forming a second SOI layer on the first SOI layer, and forming the second and fourth semiconductor devices within a silicon layer of the second SOI layer.
In yet another embodiment, the present invention includes an SRAM cell comprising a semiconductor structure having a trench disposed therein, wherein the trench extends along an axis substantially orthogonal to a top surface of the semiconductor structure. The SRAM cell also includes a first inverter formed in the semiconductor structure at a first axial location along the trench, and a second inverter formed in the semiconductor structure at a second axial location along the trench. Further, means for electrical cross-coupling is disposed within the trench, with the first and second inverters being electrically cross-coupled thereby. Thus, the electrically cross-coupled first and second inverters comprise a flip-flop.
The SRAM cell also includes an I/O transistor formed in the semiconductor structure. The I/O transistor is electrically connected to the means for electrical cross-coupling for facilitating writing to and reading from the SRAM cell. As enhancements, the means for electrical cross-coupling may comprise coaxial wiring. Furthermore, each of the two inverters may comprise a pair of FETs.
The five transistor SRAM cell of the present invention has particular advantages and features associated therewith. For instance, by forming the complete storage flip-flop of an SRAM cell in association with a single active trench structure, significant substrate space is saved. Thus, overall memory density is increased.
Moreover, the process for forming the SRAM of the present invention facilitates very well controlled vertical channel lengths. Such control is achieved by building the doped regions and channels in the substrate prior to etching the trenches. Thus, the widths of the channels and doped regions of the FET devices of the memory cell are controlled by implantation.
Further features of the present invention include the use of coaxial wiring within the active trench to electrically cross-couple the FETs of the memory cell and the inverters composed thereof. Thus, electrical cross-coupling of devices outside of the active trench is unnecessary, further reducing the substrate area necessary for the SRAM device described herein.
Therefore, a vertically oriented, high-density, five transistor (e.g. FET) SRA
Beilstein, Jr. Kenneth Edward
Bertin Claude Louis
Cronin John Edward
White Francis Roger
Chang Joni
Heslin & Rothenberg, P.C.
International Business Machines - Corporation
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