4. Active solid-state devices (e.g., transistors, solid-state diode
  5. Housing or package
  6. With semiconductor element forming part

Kenneth Edward Beilstein, Jr.

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Method and workpiece for connecting a thin layer to a monolithic

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Patent

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Method and workpiece for connecting a thin layer to a monolithic

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Patent

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Methods and apparatus for burn-in stressing and simultaneous tes

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent

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Methods and apparatus for burn-in stressing and simultaneous tes

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent

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Semiconductor chip having chip metal layer and transfer metal la

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent

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Profile ID: LFUS-PAI-P-65824

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