Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-04-14
2001-04-03
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S262000, C438S264000, C438S268000, C438S270000
Reexamination Certificate
active
06211014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to read-only memories (ROMs), and more particularly to a three-dimensional, deep-trench, high-density ROM and its manufacturing method.
2. Description of Related Art
Read-only memories (ROMs) are nonvolatile semiconductor memories used in computer and microprocessor systems for permanently storing programs and data that are repeatedly used, such as BIOS (Basic Input/Output System, used in operating systems of personal computers). ROM manufacturing involves very complicated and time-consuming processes requiring costly equipment and material. Therefore, customers typically first define the data to be permanently stored in ROMs, and then provide the data to the ROM manufacturer for programming into the ROMs. The ROM manufacturer encodes the customer programs into the ROM, before delivering back the coded ROM to the customers.
A major issue for ROM manufacturers is reducing the occupation of ROM components on a surface of a semiconductor wafer, so to lower cost and increase market share. However, in conventional ROMs, the gates comprise polysilicon layers formed above the wafer surface. Gate formation necessitates the use of photo-stepper machines in which the distance between two gate polysilicon layers cannot be reduced in an efficient manner, increasing the surface area occupation of ROM components as well as manufacturing costs. Further, conventional ROM manufacturing requires ion implantation after encoding, which generates an alignment shift that leads to transistor cell leakage problems.
A conventional ROM structure is shown in
FIGS. 1A-1C
.
FIG. 1A
is a top view,
FIG. 1B
is a cross-sectional view taken along line IB—IB of the ROM of
FIG. 1A
, and
FIG. 1C
is a cross-sectional view taken along line IC—IC of the ROM of FIG.
1
A.
Conventional ROM manufacturing includes forming source/drain regions
11
above a substrate
10
, and then forming a gate oxide layer
12
and a polysilicon gate region
13
above source/drain regions
11
. Regions
11
are referred to as “source/drain region” since they can act as either a source or a drain terminal depending upon the actual assignment of metallic wiring connections. Conventional ROM manufacturing further comprises forming a transistor in areas
14
enclosed by the dashed lines of FIG.
1
A.
When programming is required, referring to
FIG. 1C
, ROM formation further comprises coating a photoresist layer
15
on polysilicon gate region
13
, exposing only areas of the transistor cells where a permanent OFF-state is desired, and switching off a channel region
16
using an ion implantation operation. Since polysilicon gate regions
13
are all formed above the same planar surface of substrate
10
, a definitive distance is required to isolate gate regions
13
. Hence, the surface area occupation of the ROM cannot be reduced.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a three-dimensional, deep-trench, high-density ROM through which misalignment problems generated by imprecise focusing are avoided, reducing memory cell leakage and breakdown of the source/drain regions. It is a further object of the present invention to provide a three-dimensional ROM that greatly reduces its surface area occupation and leads to a reduction in production cost.
Still further object of the present invention is to provide a manufacturing method for forming a three-dimensional, deep-trench, high-density ROM.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention comprises a three-dimensional, deep-trench, high-density ROM, including: a plurality of parallel bit lines formed in a silicon substrate; a plurality of word lines running perpendicular to and above the bit lines; and a plurality memory cells, each memory cell being formed at a junction of two adjacent bit lines and a portion of one of the word lines, wherein the plurality of memory cells include a plurality of OFF-state non-conducting memory cells and a plurality of ON-state conducting memory cells, and wherein a channel region of each non-conducting memory cell has a trench depth greater than the depth of the plurality bit lines.
The present invention further comprises a method for manufacturing a three-dimensional, deep-trench, high-density ROM, the method including the steps of: performing ion implantation to form a plurality of parallel bit lines on a surface of a silicon substrate;
forming a photoresist layer to expose a plurality of channel regions of the substrate where non-conducting memory cells are desired; performing an etching operation, using the photoresist layer as a mask, to form a trench in each of the channel regions, each trench having a trench depth larger than a depth of each of the bit lines; sequentially forming a gate oxide layer and a polysilicon layer on the surface of the silicon substrate; and defining the gate oxide and polysilicon layers to form a plurality of word lines that are perpendicular to the plurality of bit lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4207585 (1980-06-01), Rao
patent: 5214303 (1993-05-01), Aoki
patent: 5329148 (1994-07-01), Aoki
patent: 5455190 (1995-10-01), Hsu
patent: 5652162 (1997-07-01), Liao
patent: 5851879 (1998-12-01), Lin et al.
patent: 5895242 (1999-04-01), Wen
patent: 5933748 (1999-08-01), Chou et al.
patent: 5973375 (1999-10-01), Baukus et al.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Guerrero Maria
Jr. Carl Whitehead
United Microelectronics Corp.
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