Thin film transistor array panel and fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S151000, C257SE21414

Reexamination Certificate

active

11486330

ABSTRACT:
The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

REFERENCES:
patent: 7253035 (2007-08-01), Kwak
patent: 2002/0117691 (2002-08-01), Choi et al.
patent: 6-69236 (1994-03-01), None
patent: 6-267983 (1994-09-01), None
patent: 2000-56284 (2000-02-01), None
patent: 2004-119923 (2004-04-01), None
patent: 1999-0066167 (1999-08-01), None
patent: 2001-0091799 (2001-10-01), None
Patent Abstracts of Japan, Publication No. 06-069236, Mar. 11, 1994, 1 page.
Patent Abstracts of Japan, Publication No. 2004-119923, Apr. 15, 2004, 1 page.
Patent Abstracts of Japan, Publication No. 06-267983, Sep. 22, 1994, 1 page.
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Korean Patent Abstract of Publication No. 1999-0066167, Aug. 16, 1998, 1 page.
Korean Patent Abstract, Publication No. 1020010091799 A, Oct. 23, 2001, 1 page.

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