Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-12-30
2001-03-06
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S676000, C257S707000, C257S675000
Reexamination Certificate
active
06198171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a “thermally enhanced quad flat non-lead package” of semiconductor., and more particularly to a “thermally enhanced quad flat non-lead package of semiconductor” for improving the heat-dissipating effect of the package.
2. Description of Related Art
In the information explosion of the world nowadays, the integrated circuit has become indispensable in our daily life, regardless of our daily life in food, clothing, lodging, transportation, education, and entertainment, the product assembled by various integrated circuit devices can be found everywhere. Following the evolution of the electronic technology, more sophisticate electronic products with user friendly and complicated functions are continuously progressing and changing. Nevertheless, in order to provide an ongoing convenience and comfortable usage, all the products are heading for the design trend of “Light, Thin, Short, and Small”. In additions, the fabrication process of semiconductor has stepped into the mass production era of 0.18 &mgr;m integrated circuit, and semiconductor products with even higher integration have become at hands easily. As for packaging technology of the back stage, there are many successful cases on the development of precise package structure, i.e. chip scale package (CSP), wafer level package, and Multi-Chip Module (MCM) etc. However, in the respect of the assembly technology of devices, there is also a multi-level printed circuit board (PCB) with even higher density which make the integrated circuit (IC) package even closely and densely dispose on the printed circuit board.
FIG. 1
is a cross-sectional view of a Quad Flat Non-Lead package of a semiconductor according to the prior art and
FIG. 2
is a bottom view corresponding to
FIG. 1
according to the prior art. As shown in FIG.
1
and
FIG. 2
, the structure of the Quad Flat Non-Lead package which has disclosed in the U.S. Pat. No. 5,942.794 (Matsushita, 1999) is constructed on a lead frame and is having a die pad
100
surrounded by a plurality of leads
102
. The chip
104
includes an active surface
106
and a back surface
108
. And a plurality of bonding pads
110
for external connections of the chip
104
is set up on the active surface
106
. The chip
104
has its back surface
108
bonded to the die pad
100
by the use of an adhesive
112
while the bonding pads
110
are electrically connected to the top surface
118
a
of the leads
102
by the use of bonding wires
114
. What is more, the molding compound
116
normally encapsulates the whole chip
104
, die pad
100
, bonding wire
114
, and the top surface
118
a
of the lead
102
while exposes the bottom surface
118
b
and the side surface
118
c
of the leads
102
. The leads
102
are used for external connections of the whole package structure
120
.
In the conventional structure of the Quad Flat Non-Lead package, the die pad
100
is upward offset in order to make the chip
104
and leads
102
positioned at different level of surfaces. An object of the upward offset of the die pad
100
is that the package can be applied in a relatively large chip in order to increase the packaging density, while the other object is to increase the bondability between the molding compound
116
and the lead frame. However, because of the demand for diminishing the thickness of the package, this conventional package structure is apt to expose the bonding wire
114
while encapsulating, thereby, the yield of the product become lower. Additionally, as the operating speed of the device of the integrated circuit becomes faster and faster nowadays. the heat generated increases accordingly, and since the conventional package structure is unable to provide a better way of heat dissipation, the performance of the electronic device will be affected.
SUMMARY OF THE INVENTION
Therefore, it is the first objective of the present invention to provide a thermally enhanced quad flat non-lead package to improve the heat-dissipating effect of the package.
It is the second objective of the present invention to provide a thermally enhanced quad flat non-lead package capable of raising the yield.
It is the third objective of the present invention to provide a Quad Flat Non-Lead package to increase the packaging density.
In order to attain the foregoing and other objectives, the present invention provides a thermally enhanced quad flat non-lead package of semiconductor that comprises a chip, a plurality of leads, and a molding compound. The chip has its active surface bonded to the top surface of the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface of the chip. The leads are disposed at the periphery of the die pad wherein the bottom surface of the lead has a stepped structure with a relatively thin portion to form a wire-bonding protruded zone. A plurality of bonding wires is used to electrically connect the wire-bonding protruded zone of the leads to the bonding pads of the chip. The molding compound encapsulates the chip, bonding wires, the die pad, and a portion of the surface of the leads, but exposes the bottom surface of the die pad. In this way, the encapsulating process makes the side surface of the lead, and the portion excluding the, vire-bonding protruded zone of the bottom surface of the lead exposed in order to make the lead become the external connecting points of the package structure.
According to a preferred embodiment of the present invention, the back surface of the chip can add a heat spreader to further improve the heat-dissipating effect.
Furthermore, in order to attain the foregoing and other objectives. the present invention also provides a stacked-chip thermally enhanced quad flat non-lead package that comprises a first chip and a second chip bonded back to back each other. The first chip has a first active surface and a first back surface while the second chip has a second active surface and a second back surface. A die pad having an area smaller than that of the first chip is bonded to the first active surface of the first chip, and the bonding pad of the first chip is exposed. A plurality of leads is disposed at the periphery of the die pad with its bottom surface appears a stepped structure which make each of the leads form a protruded wire-bonding protruded zone with a relatively thin portion.
The leads are electrically connected to the bonding pads of the first chip and the second chip respectively. The bonding pads of the first chip are connected to the protruded wire-bonding protruded zone of the bottom surfaces of the leads while the bonding pads of the second chip are connected to the top surface of the leads. Then, a molding compound is used to encapsulate the first chip, the second chip, the die pad, the bonding wires, and a portion of the surface of the lead but to expose the bottom surface of the die.pad. In additions, a portion of the bottom surface excluding the protruded wire-bonding protruded zone is also exposed.
REFERENCES:
patent: 5302849 (1994-04-01), Cabvasin
patent: 5521429 (1996-05-01), Aono et al.
patent: 5900676 (1999-05-01), Kweon et al.
patent: 5973388 (1999-10-01), Chew et al.
patent: 5977613 (1999-11-01), Takata et al.
patent: 6025640 (2000-02-01), Yagi et al.
patent: 6075284 (2000-06-01), Choi et al.
Huang Chien-Ping
Ko Eric
Clark Sheila V.
Huang Jiawei
J C Patents
Siliconware Precision Industries Co., LTD.
LandOfFree
Thermally enhanced quad flat non-lead package of semiconductor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thermally enhanced quad flat non-lead package of semiconductor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thermally enhanced quad flat non-lead package of semiconductor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2479226