Thermal CVD process for depositing a low dielectric constant...

Details Thermal CVD process for depositing a low dielectric constant... Thermal CVD process for depositing a low dielectric constant...

2000-08-07

2003-08-05

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000, C438S779000

Reexamination Certificate

active

06602806

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the formation of dielectric layers during fabrication of integrated circuits on semiconductor wafers. More particularly, the present invention relates to a method for providing a dielectric film having a low dielectric constant that is particularly useful as a premetal or intermetal dielectric layer.
One of the primary steps in the fabrication of modem semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or “CVD.” Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma enhanced CVD techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio frequency (RF) or microwave energy. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Today's fabrication plants are routinely producing devices having 0.25 &mgr;m and even 0.1 &mgr;m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries. In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having a low dielectric constant. Low dielectric constant films are particularly desirable for premetal dielectric (PMD) layers and intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metalization, to prevent cross-talk between the different levels of metalization, and to reduce device power consumption. Undoped silicon oxide films deposited using conventional CVD techniques may have a dielectric constant (k) as low as about 4.0 or 4.2. One approach to obtaining a lower dielectric constant is to incorporate fluorine in the silicon oxide film. Fluorine-doped silicon oxide films (also referred to as fluorine silicate glass or —“FSG” films) may have a dielectric constant as low as about 3.4 or 3.6. Despite this improvement, films having even lower dielectric constants are highly desirable for the manufacture of integrated circuits using geometries of 0.1 8 &mgr;m and smaller. Numerous films have been developed in attempts to meet these needs including: a spin-on glass called HSQ (hydrogen silsesqui-oxane, HSiO
1.5
) and various carbon-based dielectric layers, such as parylene and amorphous fluorinated carbon. Other low-k films have been deposited by CVD using an organosilane precursor and oxygen to form a silicon-oxygen-carbon (Si—O—C) layer.
While the above types of dielectric films are useful for some applications, manufacturers are always seeking new and improved methods of depositing low-k materials for use as IMD and other types of dielectric layers.
SUMMARY OF THE INVENTION
The method of the present invention provides such a new and improved low-k material deposition process. The process is particularly useful in the manufacture of sub-0.2 micron circuits as it can form a PMD or IMD film with a dielectric constant below 3.0. The film has good gap fill capabilities, high film stability and etches uniformly and controllably when subject to a chemical mechanical polishing (CMP) step.
The method of the present invention deposits a carbon-doped silicon oxide layer using a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process, the substrate is heated to a temperature less than about 250° C.
In some currently preferred embodiments the organosilane precursor has a formula of Si(CH
3
)
x
H
4-x
where x is either 3 or 4 making the organosilane precursor either trimethylsilane (TMS) or tetramethylsilane (T4MS). In other preferred embodiments, the substrate over which the carbon-doped oxide layer is deposited is heated to a temperature of between about 150-200° C. and the deposition is carried out in a vacuum chamber at a pressure of between 1-760 Torr. In still other preferred embodiments, the carbon-doped silicon oxide layer is cured after it is deposited to minimize subsequent moisture absorption. Curing can be done in either a vacuum or conventional furnace environment.
In one specific embodiment, the process gas is a mixture of TMS, ozone and helium. Deposition pressure in this embodiment can be any pressure between 1-760 Torr, but the flow rate of the TMS source is selected so that the partial pressure of TMS is less than its vapor pressure in the deposition environment. In a preferred version of this embodiment, after film deposition is substantially completed, the ozone flow into the deposition chamber is stopped at least several seconds prior to the flow of TMS in order to ensure that residual ozone in the chamber reacts, in the gas phase, with the TMS and not with carbon in the deposited film.
Optionally, one or more dopants, such as phosphorous and/or boron, may be included in the process gas to enhance the properties of the deposited film. In some embodiments of the present invention, the carbon-doped layer is capped with a layer of silicon oxide or silicon nitride. In one specific embodiment the carbon-doped layer is capped with a layer of PECVD silicon oxide. Furthermore, the carbon-doped layer may be formed by a two-step process. In one embodiment a first portion of the carbon-doped layer is formed at a high pressure and low temperature to provide good gap-fill. A second portion of the carbon-doped layer is then formed at a high temperature and a low pressure to provide a high deposition rate. Alternatively a second portion may be formed using PECVD to provide a compressive stress that partially compensates for a tensile stress in the thermally deposited layer.
These and other embodiments of the present invention, as well as its advantages and features, are described in more detail in conjunction with the text below and attached figures.


REFERENCES:
patent: 5314724 (1994-05-01), Tsukune et al.
patent: 5314845 (1994-05-01), Lee et al.
patent: 5338362 (1994-08-01), Imahashi
patent: 5532191 (1996-07-01), Nakano et al.
patent: 5560777 (1996-10-01), Ahn
patent: 5605867 (1997-02-01), Sato et al.
patent: 5610105 (1997-03-01), Vines et al.
patent: 5661093 (1997-08-01), Ravi et al.
patent: 5741740 (1998-04-01), Jang et al.
patent: 5744196 (1998-04-01), Laxman et al.
patent: 5776603 (1998-07-01), Zagdoun et al.
patent: 5812403 (1998-09-01), Fong et al.
patent: 5820976 (1998-10-01), Kamo
patent: 5872065 (1999-02-01), Sivaramakrishnan
patent: 5900290 (1999-05-01), Yang et al.
patent: 5989983 (1999-11-01), Goo et al.
patent: 5994209 (1999-11-01), Yieh et al.
patent: 6054379 (2000-04-01), Yau et al.
patent: 6068884 (2000-05-01), Rose et al.
patent: 6114216 (2000-09-01), Yieh et al.
patent: 6149987 (2000-11-01), Perng et al.
patent: 6159871 (2000-12-01), Loboda et al.
patent: 6171945 (2001-01-01), Mandal et al.
patent: 6225236 (2001-05-01), Nishimoto et al.
patent: 6255222 (2001-07-01), Xia et al.
patent: 6348421 (2002-02-01), Shu et al.
patent: 2001/0005546 (2001-06-01), Cheung et al.
patent: 196 54 737 (1997-07-01), None
patent: 199 04 311 (1999-08-01), None
patent: 421 203 (1991-04-01), None
patent: 721 019 (1996-07-01), None
patent: 774 533 (1997-05-01), None
patent: 0 884 401 (1998-12-01), None
patent: 3-166726 (1991-07-01), None
patent: 4-116927 (1992-04-01), None
patent: 9-237785 (1997-09-01), None
patent: 9-246377 (1997-09-01), None
patent: WO 99/19910 (1999-04-01), None
S. Nag et al., “Carbon Doped Silicon Oxide Films for Sub-0.25 &mgr;m Technology Interconnect Isolation,”Novellus Systems, Inc., San Jose, CA,pp. 74-78 (date ??).
A. Nara et al., “Low Dielectric Constant Insulator Formed by Downstr

Affiliated with

Also associated with

Rating

Thermal CVD process for depositing a low dielectric constant... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thermal CVD process for depositing a low dielectric constant..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thermal CVD process for depositing a low dielectric constant... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3087566