Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-03-15
2011-03-15
Ton, David (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
07908536
ABSTRACT:
Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.
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USPTO U.S. Appl. No. 11/380,677, Image File Wrapper printed May 18, 2010, 2 pages.
USPTO U.S. Appl. No. 11/421,515, Image File Wrapper printed May 18, 2010, 2 pages.
Chelstrom Nathan P.
Ferguson Steven R.
Riley Mack W.
International Business Machines - Corporation
Talpis Matthew B.
Ton David
Walder, Jr. Stephen J.
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