Tester architecture construction data generating method,...

Details Tester architecture construction data generating method,... Tester architecture construction data generating method,...

2005-05-03

2005-05-03

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

06889348

ABSTRACT:
The present invention provides a test circuit configuration technology suitable for use in a semiconductor device, which is capable of testing the semiconductor device without using a commercially-available tester (test device) and is less reduced in required cost. A test program related to a semiconductor device to be tested, which is described in tester language, is analyzed. Components of a test circuit (ALPG), corresponding to the contents of each test to be carried out are extracted, i.e., unwanted or unnecessary components are deleted to thereby generate the description (test circuit architecture construction data) of a circuit capable of conducting tests in desired test units according to HDL (Hardware Description Language).

REFERENCES:
patent: 5883905 (1999-03-01), Eastburn
patent: 5931953 (1999-08-01), Lesmeister
patent: 5935256 (1999-08-01), Lesmeister
patent: 6357027 (2002-03-01), Frankowsky

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