Test system for conducting parallel bit test

Details Test system for conducting parallel bit test Test system for conducting parallel bit test

2011-07-12

2011-07-12

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S042000

Reexamination Certificate

active

07979760

ABSTRACT:
Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.

REFERENCES:
patent: 6415397 (2002-07-01), Co et al.
patent: 6593763 (2003-07-01), Weber
patent: 6762615 (2004-07-01), Lee et al.
patent: 2008/0065933 (2008-03-01), Thayer
patent: 2005-078603 (2005-03-01), None
patent: 10-2001-0112540 (2001-12-01), None
patent: 20-0287948 (2002-08-01), None

Affiliated with

Also associated with

Rating

Test system for conducting parallel bit test does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test system for conducting parallel bit test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test system for conducting parallel bit test will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2631634