Test structure of DRAM

Details Test structure of DRAM Test structure of DRAM

2005-05-10

2005-05-10

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S304000, C257S302000, C257S301000

Reexamination Certificate

active

06891216

ABSTRACT:
A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.

REFERENCES:
patent: 4905065 (1990-02-01), Selcuk et al.
patent: 4921815 (1990-05-01), Miyazawa
patent: 5225698 (1993-07-01), Kim et al.
patent: 5250829 (1993-10-01), Bronner et al.
patent: 5264716 (1993-11-01), Kenney
patent: 5798545 (1998-08-01), Iwasa et al.
patent: 20030178661 (2003-09-01), Tzeng et al.

Affiliated with

Also associated with

Rating

Test structure of DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test structure of DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test structure of DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3427938