Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1997-07-14
1999-05-04
Chaudhuri, Olik
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
438 17, H01L 2358
Patent
active
059006447
ABSTRACT:
The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.
REFERENCES:
patent: 5229309 (1993-07-01), Kato
patent: 5451529 (1995-09-01), Hsu et al.
patent: 5494697 (1996-02-01), Blayo et al.
patent: 5780870 (1998-07-01), Maeda et al.
Chen Jue-Jye
Huang Yuan-Chang
Mii Yuh-Jier
Ying Shu-Lan
Ackerman Stephen B.
Chaudhuri Olik
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company , Ltd.
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