4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Takehiro Masumoto

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Micro computer and method of optimizing microcomputer

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Semiconductor chip and semiconductor device including the same

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate

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Test pattern generating method and test pattern generating syste

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Profile ID: LFUS-PAI-P-1616312

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