Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-28
2004-06-15
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S032000, C324S073100, 37
Reexamination Certificate
active
06751767
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a technique for generating test patterns for logic circuits and, more particularly, to a method and apparatus for compressing test patterns which detect faults in logic circuits.
BACKGROUND OF THE INVENTION
Increases in the scale of large-scale integration generally is accompanied by use of a method wherein a test pattern generating process which generates test patterns for detecting faults in logic circuits such as logical LSI devices is provided with a pattern compression processing step for reducing the pattern length of the test patterns, without lowering the fault detection rate of the test patterns, before the generated test patterns are supplied to the LSI tester. According to this method, it is the test patterns compressed by the pattern compression step that are supplied to the LSI tester. The reason for adopting this method is that higher integration and functionality of LSI devices is associated with test patterns of larger scale, making it necessary to compress the test patterns in advance in order to raise testing efficiency so as to overcome limitations on test-pattern memory (local memory) with which the LSI tester is equipped.
Conventionally, test pattern compression is carried out by assigning an undefined value (also referred to as an “indeterminate value”) X (Don't Care), which will not lower fault detection performance, to the fault-detection test patterns and trying pattern merging in accordance with prescribed rules on a plurality of test patterns to which the undefined value X has been assigned. A known method of assigning the undefined value X to fault detection test patterns is to assign the undefined value X to input pins that do not participate in fault detection, e.g., input pins that do not possess paths to an output pin at which a fault has been detected.
A test pattern comprises rows and columns, and the number of a row starting from the first row is referred to as the “pattern number”. The columns correspond to the pins of the logic circuit. The pattern of the first row is applied simultaneously to the input pins of the device (logic circuit) undergoing testing in the LSI tester. This pattern is referred to also as a “test vector”. The pattern applied to the input pins of the device being tested is treated as a test pattern.
A fault model of a logic circuit and assignment of the undefined value X to test patterns will be described below. The fault dealt with in a logic-circuit fault simulation is a modeled logical fault. The model usually used is a simple degenerate fault model. The simple degenerate fault model has such a fault that the output of a gate circuit, for example, is always fixed at 0 (a 0 degeneracy fault, or “stuck at 0”) or at 1 (a 1 degeneracy fault, or “stuck at 1”) regardless of the input to the gate circuit.
Faults in a logic circuit will be discussed in general taking as an example a combinational circuit illustrated in FIG.
10
A. This combinational circuit. is such that when the output of an OR gate OR
2
has developed a 1 degeneracy fault (stuck at 1) Sa
1
, the output of this OR gate is always “1” and never “0” even when the input side thereof is supplied with a pattern that should make the output “0”. Accordingly, with regard to a pattern for detecting the fact that the output of the OR gate OR
2
is stuck at 1, it is necessary to detect that the OR gate OR
2
outputs “1” when “0” is applied to both inputs of the OR gate OR
2
. To achieve this, it is required to make (
0
,
0
) the two inputs to the OR gate OR
2
and to make “1” the output of an OR gate OR
3
whose output is connected to one input terminal of an AND gate AND
6
the other input terminal of which has the output of OR gate OR
2
connected thereto. It will suffice to make (
0
,
0
) the two inputs to an OR gate OR
1
, which will output “0”, and to make “0” one of the two inputs to the AND gate AND
3
. For this it will suffice to make “0” one of the two inputs of each of AND gates AND
1
, AND
2
whose output terminals are connected to the input side of the OR gate OR
1
. Further, it will suffice to make “1” one of the two inputs to the OR gate OR
3
. If the output of an AND gate AND
4
has been made “1”, then it will suffice to make “1” both inputs to the AND gate AND
4
and to make “0” or “1” the output of an AND gate AND
5
.
In order to compress test patterns for detecting faults in a logic circuit, the undefined value X is assigned to input pins for which it does not matter whether the assigned values are “0” or “1”. In a case where an undefined value X in a test pattern is input to an LSI tester, the value is set to “0” or “1”.
In order to detect the Sa
1
fault at the output of the OR gate OR
2
, the test pattern applied to input pins I
1
-I
10
of the logic circuit is made “
0100101101
”, as shown in FIG.
10
A. However, since the input pins I
2
, I
3
, I
9
and I
10
play no part in fault detection, undefined values X are assigned to these pins. As a result, the generated test pattern will be “0XX0X011XX”. The test pattern with the assigned undefined values X is merged with other test patterns in the row direction in accordance with a predetermined rule, whereby compression is achieved. Processing for achieving pattern merging will be described in detail later.
Another method of compressing a test pattern known in the art is to switch the order of test patterns.
DISCUSSION ON THE RELATED ART
The configuration and operation of a system used in compressing test patterns according to the related art will now be described.
FIG. 8
illustrates a system configuration according to a related art. In an information processor (referred to as a “local CPU”)
10
A which executes pattern compression processing, circuit information
301
concerning a logic circuit to be tested is read into the system by circuit information read-in means
304
, fault information
302
is read into the system by fault information read-in means
305
, a test pattern (pattern information)
303
is read into the system by pattern information read-in means
306
and a repeated random-number fault simulation is run for all faults. The test pattern
303
to be compressed is created automatically by ATPG (Automatic Test Pattern Generation), semi-automatically or manually. If the information composed of the circuit information
301
, fault information
302
and pattern information
303
has been stored in a file unit, then the read-in means
304
,
305
,
306
constitute input means for inputting the information from the file unit. On the other hand, if the information composed of the circuit information
301
, fault information
302
and pattern information
303
resides in a server or the like (not shown) connected to a network, then the read-in means
304
,
305
,
306
constitute communication means for downloading the circuit information
301
, fault information
302
and pattern information
303
from the server.
The fault information
302
comprises a list of paired information, namely faults and fault insertion points (node information) in logic circuit. As mentioned earlier, the fault dealt with in the fault simulation is the logical fault Sa0 (stuck at 0) or Sa1 (stuck at 1).
A random-number fault simulation assigns “0” or “1” to undefined values in a test pattern-using random numbers, thereby activating the undefined values to carry out the fault simulation.
More specifically, in order to perform pattern compression by pattern merging, undefined values X are inserted into the test pattern, which has been read into the system by the pattern-information read-in means
306
, at locations that are not necessary for fault detection, as described earlier.
By assigning “0” or “1” to the undefined values X in this test pattern, the undefined values are activated to remove them from within the logic circuit undergoing inspection. Using pseudo-random numbers generated based upon random-number-sequence initial-value information
308
set by random-number-sequence initial-value setting means
307
, means
309
for generating random numbers
NEC Electronics Corporation
Ton David
Whittington Anthony T.
Young & Thompson
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