Test mode for a self-refreshed SRAM with DRAM memory cells

Details Test mode for a self-refreshed SRAM with DRAM memory cells Test mode for a self-refreshed SRAM with DRAM memory cells

2005-12-27

2005-12-27

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S745000, C365S201000, C365S222000

Reexamination Certificate

active

06981187

ABSTRACT:
A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a test-mode enable circuit, an arbitration circuit, and a memory control logic circuit. In a normal mode of operation, the test mode enable circuit is not active. In a test mode of operation, the test mode enable circuit is active which enables the memory control logic to be controlled by an external command signal that is provided through an external pin, such as a chip-enable /CE pin when the chip is in the test mode.

REFERENCES:
patent: 5295109 (1994-03-01), Nawaki
patent: 6388934 (2002-05-01), Tobita
patent: 6501693 (2002-12-01), Takatsuka et al.
patent: 6657901 (2003-12-01), Kajigaya et al.
patent: 6834020 (2004-12-01), Takahashi et al.
patent: 2003/0198116 (2003-10-01), Sato et al.

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