Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-06-23
2004-11-02
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S301000, C257S304000, C257S620000, C257S532000, C438S014000, C438S243000, C438S386000, C438S462000
Reexamination Certificate
active
06812487
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test key and particularly to a test key and method for validating the doping concentration of buried layers within a deep trench capacitors.
2. Description of the Prior Art
Trench capacitors are frequently implemented as the essential charge storage device in a DRAM (Dynamic Random Access Memory). The trench capacitor is formed in the substrate and has a capacitance proportional to the depth of the trench. That is to say, by increasing the depth of the trench, which results in the “plates” occupying a larger surface area, the trench capacitor provides a higher capacitance.
FIG. 1
is a diagram showing the layout of a conventional DRAM. A trench capacitor
10
is disposed below the passing wordline. A transistor
14
is coupled to a node
16
of the trench capacitor
10
through a diffusion region
18
. A diffusion region
20
is coupled to a plug
22
. The plug
22
is coupled to a bitline (not shown). Thus, data is read from or written into the trench capacitor
10
through the node
16
by operation of the transistor
14
. The transistor
14
is controlled by voltages on the wordline
12
. When a high voltage level is on the wordline
12
, a conductive channel is formed below the wordline
12
so that a current flows from or to the node
16
through the diffusion regions
18
and
20
, whereby the data is read from or written into the capacitor
10
.
FIG. 2
shows a cross section along the line AA in FIG.
1
. An STI (Shallow Trench Isolation)
28
is formed in the substrate and trench capacitor to define an active area and isolate the trench capacitor
10
from the subsequently formed wordline
12
. After formation of the wordline
12
, the diffusion regions
18
and
20
, used as a source and drain, on two sides of the wordline
12
are formed by ion implantation with masking of the wordline
12
and STI
28
. The channel length L of the transistor
14
corresponds to the size of the wordline
12
and the profiles of the diffusion regions
18
and
20
. Further, the profiles of the diffusion regions
18
and
20
are based on the doping concentration of the storage node
16
composed of conducting layers L
13
and L
12
, and an electrode layer L
11
. Accordingly, the doping concentrations of the layers L
11
, L
12
and L
13
have great impact on the channel length L of the transistor
14
. For DRAM employing trench capacitors as storage devices, an invalid doping concentration in the storage node results in current leakage adjacent memory cells or even defective cells. Validation of the doping concentration of the storage node is an essential step for DRAM manufacturing.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a test key and method for validating the doping concentration of buried layers within the deep trench capacitor.
The present invention provides a test key comprising a trench capacitor deposited in the scribe line region with an electrode layer of a first doping concentration, a first conducting layer with a second doping concentration and a second conducting layer with a third doping concentration, an isolation region deposited in the trench capacitor, penetrating the second conducting layer and extending into the first conducting layer so that the second conducting layer is divided into a first and second portion, a first plug coupled to a first side of the first portion of the second conducting layer, a second plug coupled to a second side of the first portion of the second conducting layer, and a third plug coupled to the second portion of the second conducting layer.
The present invention further provides a validation method comprising the steps of providing a wafer having at least one scribe line region and a memory cell region, forming a test key in the scribe line region and a plurality of memory cells in the memory cell region, wherein the test key comprises a trench capacitor deposited in the scribe line region with an electrode layer of a first doping concentration, a first conducting layer with a second doping concentration and a second conducting layer with a third doping concentration, an isolation region deposited in the trench capacitor, penetrating the second conducting layer and extending into the first conducting layer so that the second conducting layer is divided into a first and second portion, a first plug coupled to a first side of the first portion of the second conducting layer, a second plug coupled to a second side of the first portion of the second conducting layer, and a third plug coupled to the second portion of the second conducting layer, measuring a first resistance between the first and second plug, measuring a second resistance between the second and third plug, and validating the first, second and third doping concentrations by the first and second resistance.
REFERENCES:
patent: 4390586 (1983-06-01), Lemelson
patent: 6339228 (2002-01-01), Iyer et al.
patent: 2004/0017710 (2004-01-01), Chang et al.
patent: 2004/0033634 (2004-02-01), Wu et al.
Huang Chien-Chang
Jiang Bo-Ching
Kuo Tse-Main
Ting Yu-Wei
Wu Tie-Jiang
Nanya Technology Corporation
Prenty Mark V.
Quintero Law Office
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