Test interface for memory elements

Details Test interface for memory elements Test interface for memory elements

2008-11-11

2010-11-30

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C714S726000

Reexamination Certificate

active

07844871

ABSTRACT:
A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.

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Dac C. Pham, “Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor,” pp. 1-18; Jan. 2006.

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