Test data topology write to memory using latched sense...

Details Test data topology write to memory using latched sense... Test data topology write to memory using latched sense...

2007-01-30

2007-01-30

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S201000, C365S222000

Reexamination Certificate

active

11046065

ABSTRACT:
For one or more disclosed embodiments, a test data topology may be written to memory by writing data into an initial row of memory cells. The writing of data comprises latching data in a plurality of sense amplifier latches. The initial row of memory cells is deactivated while the latched data is retained in the sense amplifier latches. Another row of memory cells is identified in accordance with a predetermined row addressing sequence for the test data topology. The other row of memory cells is activated to write the retained latched data to the other row.

REFERENCES:
patent: 5301299 (1994-04-01), Pawlowski et al.
patent: 7032119 (2006-04-01), Fung
patent: 2006/0092736 (2006-05-01), Rohleder

Affiliated with

Also associated with

Rating

Test data topology write to memory using latched sense... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test data topology write to memory using latched sense..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test data topology write to memory using latched sense... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3745194