Test apparatus and test method

Details Test apparatus and test method Test apparatus and test method

2008-07-01

2008-07-01

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S055000, C714S721000

Reexamination Certificate

active

07395480

ABSTRACT:
The present invention provides a test apparatus comprising: a threshold voltage setting unit for setting threshold voltages of a logic device component connected to the signal propagation path; a test signal supply unit for supplying a test signal to the test subject device so as to operate the logic device component provided to the signal propagation path in a state in which the threshold voltages have been set to first threshold voltages, and in a state in which the threshold voltages have been set to second threshold voltages, by the threshold voltage setting unit; a current measurement unit, for measuring a first operating current which is the current consumption of the test subject device in a case in which the logic device component operates in a state in which the first threshold voltages have been set, and for measuring a second operating current which is the current consumption of the test subject device in a case in which the logic device component operates in a state in which the second threshold voltages have been set; and an acceptability determination unit for determining whether or not the signal propagation path is acceptable, based upon the first operating current and the second operating current.

REFERENCES:
patent: 6369601 (2002-04-01), Ishigaki
patent: 6657901 (2003-12-01), Kajigaya et al.
patent: 6725404 (2004-04-01), Choudhury et al.
patent: 6828799 (2004-12-01), Higashide et al.
patent: 6873171 (2005-03-01), Reynick
patent: 7039842 (2006-05-01), Whitten et al.
patent: 7216311 (2007-05-01), Tanaka et al.
patent: 2006/0190790 (2006-08-01), Pilling et al.
J.P. Hurst, N. Kanopoulos, “Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits”, Asian Test Symposium, Nov. 23, 1995, IEEE, pp. 346-352.
K. Hatayama, M. Ikeda, M. Takaura, S. Uchiyama, Y. Sakamoto, “Application of a Design for Delay Testability Approach to High Speed Logic LSIs”, Asian Test Symposium, Nov. 17, 1997, IEEE, pp. 112-115.
N.A. Touba, E.J. McCluskey, “Applying Two-Pattern Tests Using Scan-Mapping”, IEEE VLSI Test Symposium 1996, Apr. 28, 1996, IEEE pp. 393-397.
Eric McDonald, N.A. Touba, “Delay Testing of SOI Circuits: Challenges with the History Effect”, International Test Conference 1999, Sep. 27, 1999, IEEE, pp. 269-275.
Hiroyuki Mizuno, “Increase of Leak Current Accompanying Low Voltage and High-Speed of CMOS LSI and a Technique for Reducing the Leak Current”, The Transactions of the Institute of Electronics, Information and Communication Engineers, vol. J83-C, No. 10, Oct. 2000, pp. 926-935.

Affiliated with

Also associated with

Rating

Test apparatus and test method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test apparatus and test method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test apparatus and test method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2798694