Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-11
2002-09-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
06449742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a tester and method for testing an integrated circuit.
2. Background Information
Microprocessors typically receive and transmit data through busses that are connected to memory or input/output (I/O) devices. The data signal(s) is typically latched into the processor with a clock signal.
FIG. 1
shows a timing diagram for the data and clock signals on a bus connected to a processor. The leading edge of the clock signal is generated subsequent to the leading edge of the data signal. The time period between the leading edge of the data signal and the leading edge of the clock signal is commonly referred to as the Tvb parameter. The time period between the trailing edges of the clock and data signals is commonly referred to as the Tva parameter. The Tvb parameter is the sum of a setup time required by the processor and a setup margin. The Tva parameter is the sum of a hold time required by the processor and a hold margin. The Tvb and Tva parameters are typically specified for every integrated circuit that reads data. For example, a microprocessor and accompanying bus will have a Tvb and Tva specification. When manufacturing microprocessors, it is desirable to test the individual processors to determine compliance with the Tvb and Tva design parameters.
FIG. 2
shows a tester or automatic test equipment (ATE)
1
of the prior art that is used to determine whether a microprocessor
2
meets the required Tvb and Tva design specifications. The ATE
1
may be connected to both a frontside bus
3
and a backside bus
4
of the processor
2
. The ATE
1
may write data to the processor
2
through the frontside bus
3
. The processor
2
may then write the same data back to the ATE
1
through the backside bus
4
. The ATE
1
determines the relative positions of the leading and trailing edges of the data and clock signals received from the processor
2
to determine the Tvb and Tva values. The ATE
1
then compares the actual Tvb and Tva values with the Tvb and Tva design values to determine if the processor meets the specification.
Microprocessors are continuously being designed to operate at higher speeds. To effectively test the new designs the ATE must be upgraded to operate at the higher frequencies. Upgrading the ATE can be expensive and increase the cost of testing the integrated circuits. Additionally, there is typically an error associated with measuring the edges of the signals and the corresponding Tva and Tvb parameters. The errors reduce the accuracy of the test and thus increase product cost by reducing yield. It would be desirable to provide a tester and method for testing an integrated circuit that is relatively independent of the circuit operating speed.
Integrated circuits are typically assembled into packages that are mounted to a printed circuit board. The integrated circuits are typically tested after being assembled into the package but before being mounted to the printed circuit board. The ATE may have a plurality of spring loaded pogo pins that engage the electrical contacts of the package. For the above described microprocessor the tester must have pogo pins for both the frontside and backside busses. The cost of the tester is proportional to the number of pogo pins. It would be desirable to provide a tester for a frontside/backside processor that eliminated some of the pogo pins required to test the processor.
SUMMARY OF THE INVENTION
One embodiment of the present invention is an apparatus for testing a device under test (DUT) that can be coupled to a secondary device. The ATE may have a frontside bus coupled to the DUT and a backside bus coupled to the DUT and the secondary device.
REFERENCES:
patent: 5621741 (1997-04-01), Kohiyama
patent: 5831994 (1998-11-01), Takino
patent: 5889936 (1999-03-01), Chan
patent: 6243841 (2001-06-01), Mydill
patent: 6311300 (2001-10-01), Omura et al.
patent: 6324665 (2001-11-01), Fay
Andrew Gary
Arabi Tawfik
Eberlein Greg
Pedarla Srirama
Riendeau Dave
Blakely , Sokoloff, Taylor & Zafman LLP
De'cady Albert
Dooley Matt
Intel Corporation
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