Method of planarizing peripheral circuit region of a DRAM

Details Method of planarizing peripheral circuit region of a DRAM Method of planarizing peripheral circuit region of a DRAM

2001-03-09

2002-04-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S254000, C438S255000, C438S396000, C438S397000, C438S398000

Reexamination Certificate

active

06372572

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method of planarizing the peripheral circuit region of advanced DRAM.
2. Description of Related Art
FIGS. 1A through 1G
are schematic cross-sectional views showing the progression of steps for producing a conventional crown-shaped capacitor in 0.21/0.18 &mgr;m DRAM. First, as shown in
FIG. 1A
, a silicon oxide layer
101
and a silicon nitride layer
102
are sequentially formed over a substrate
100
. After polysilicon plugs
104
are formed in the silicon nitride layer
102
and the silicon oxide layer
101
, a patterned silicon oxide layer
106
is formed over the silicon nitride layer
102
. As shown in
FIG. 1B
, a conformal doped amorphous silicon layer
108
is formed over the exposed silicon nitride layer
102
and the silicon oxide layer in the crown-shaped capacitor region
120
. The doped amorphous silicon layer
108
also covers the silicon oxide layer
106
in the peripheral circuit region
122
. As shown in
FIG. 1C
, a photo resist (PR) layer
110
is formed filling the crown-shaped capacitor region
120
and the peripheral circuit region
122
. The PR layer
110
protects a portion of the doped amorphous silicon layer
108
in a subsequent operation. As shown in
FIG. 1D
, chemical-mechanical polishing is carried out to polish the PR layer
110
and to remove a portion of the doped amorphous silicon layer
108
, thereby forming the lower electrodes
112
of various capacitors that are separated from each other. As shown in
FIG. 1E
, after removal of the PR layer
110
, the silicon oxide layer
106
is recessed by performing a wet chemical etch process. Simultaneously, the remaining portion of the oxide layer
106
in the peripheral circuit region
122
is also removed. As shown in
FIG. 1F
, hemispherical silicon grains
114
are sequentially formed on the sidewalls of the lower electrodes
112
. Hence, the exposed surface area of the lower electrodes
112
is increased. As shown in
FIG. 1G
, an ONO/NO dielectric layer
116
is formed over the lower electrodes
114
and the silicon nitride layer
102
. Lastly, a conductive layer
118
is formed over the dielectric layer
116
to form the upper electrode of the capacitor, thereby completing the fabrication of a conventional crown-shaped DRAM capacitor.
As shown in
FIG. 1G
, there is a height difference of about 8000 Å to 10000 Å between the lower electrodes
112
in the crown-shaped capacitor region
120
and the silicon nitride layer
102
in the peripheral circuit region
122
. Hence, planarizing the deposited upper electrode layer
118
and the peripheral circuit region
122
is difficult, and thereby produces a poor foundation for forming the desired devices in subsequent steps.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of planarizing the peripheral circuit region of an advanced DRAM. Nitrogen is implanted into the silicon dioxide layer in the peripheral circuit region to form a silicon oxy-nitride layer. The silicon oxy-nitride layer serves as a protective layer shielding the silicon dioxide layer in the peripheral circuit region from the subsequent chemical-mechanical polishing and silicon oxide layer removal. The silicon oxy-nitride layer also forms a platform in the peripheral circuit production.
A second object of this invention is to provide a method of planarizing the peripheral circuit region of an advanced DRAM that can be easily implemented.
To achieve these and other advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of planarizing the peripheral circuit region of an advanced DRAM. By implanting nitrogen into a silicon dioxide layer to form a silicon oxy-nitride layer, the problem caused by the planarization of the peripheral circuit region is thus solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5858831 (1999-01-01), Sung
patent: 6077738 (2000-06-01), Lee et al.
patent: 6143596 (2000-11-01), Wang
patent: 6177307 (2001-01-01), Tu et al.
patent: 6200850 (2001-03-01), Wu
patent: 6255160 (2001-07-01), Huang
patent: 6258690 (2001-07-01), Zenke

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