Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-01-13
2009-11-17
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07620866
ABSTRACT:
According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.
REFERENCES:
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6886110 (2005-04-01), O'Brien
patent: 7103814 (2006-09-01), Corbin et al.
patent: 7181663 (2007-02-01), Hildebrant
patent: 7231563 (2007-06-01), Vinke et al.
patent: 7296200 (2007-11-01), Park et al.
Waayers T Ed—Institute of Electrical and Electronics Engineers: “An Improved Test Control Architecture and Test Control Expansion for Core-Based System Chips”; Proceedings International Test Conference 2003. (ITC); Charlotte NC. Sep. 30, Oct. 2, 2003; International Test Conf. N. Y.: IEEE US vol. 1, Sep. 30, 2003; pp. 1145-1154.
Zorian Y et al: “Testing Embedded-Core Based System Chips”; Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270) Int. Test Conf. Washington DC USA; Online Oct. 23, 1999 pp. 130-143.
Marinissen Erik J.
Waayers Thomas F.
Kerveros James C
NXP B.V.
LandOfFree
Test access architecture and method of testing a module in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test access architecture and method of testing a module in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test access architecture and method of testing a module in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4054688