Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-01-18
2004-06-08
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C438S017000
Reexamination Certificate
active
06747472
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to the field of microelectronics and, more particularly, to the field of fabricating and interconnecting extremely small semi-conductor devices commonly referred to as “chips.”
RELATED INVENTIONS
The present invention is related to certain inventions assigned to the assignee of the present invention. These are in co-pending applications YOR920010217US1 and 20010216US1, the disclosures of which are cross-referenced and incorporated herein.
BACKGROUND OF THE INVENTION
Increased levels of integration in the silicon transistor technology over the last two decades have facilitated the migration from large scale integrated (LSI) to very large scale integrated (VLSI) and now to ultra-large scale integrated (ULSI) circuits for use in silicon chips for computing, communication and micro controller applications. Optimum utilization of these highly integrated silicon chips requires a more space efficient packaging with supporting devices such as memory chips. Further, with the advent of mobile communication devices, hand held organizers and computing devices, there has also been a push to integrate such varied functions into a single compact system. This in turn has led to the push in the microelectronics industry towards system-on-a-chip (SOC) approach.
Simply stated, the SOC approach attempts to integrate as many of these different device functionalities on the same silicon chip so that a single large chip can provide a variety of functions to the end user. Although conceptually very attractive such an approach is practically daunting due to several reasons. First, the materials, fabrication processes and feature sizes optimum for the different microelectronic devices (such as memory chips, logic chips, wireless communication chips, etc.) are quite different from each other. Combining them all onto the same chip implies making compromises that can limit the performance achievable in each of the device blocks in the SOC. Second, integration of a large number of functional blocks requires a large chip size with many levels of wiring constructed on the chip. Both these factors tend to reduce the yield and increase the cost per chip, which is undesirable. Third, one has to design and build every unique combination of functions (e.g., memory and microprocessor, wireless communication and microprocessor, etc.) leading to a large variety of chip part numbers and product mix that is not conducive to low cost reduced manufacturing. Last, the expertise required for combining a diverse set of materials, process and integration schemes on a single SOC is often not available in a single enterprise as these are currently part of different microelectronic businesses.
An attractive alternative to SOC is system-on-a-package or SOP wherein a number of chips, each optimized for its unique function and perhaps manufactured in different factories specially tailored to produce the specific chips are combined on a first level packaging carrier that interconnects them and allows the resulting package to function as a single system. The level of interconnection and input-output-(I/O) density required in such a package is expected to be far greater than those currently available in printed circuit board or multilayer ceramic technologies. Since this SOP carrier with chips assembled on it is expected to replace an SOC, it is reasonable to expect that the interconnect and I/O densities should be somewhere between those used in the far back end of the line (FBEOL) interconnect levels on chips (typically wiring and vias on 500 nm to 1000 nm pitch) and the most aggressive packaging substrates (typically vias and wiring on 10,000 to 20,000 nm pitch). Extension of the FBEOL processes at the required wiring size and pitch for the SOP carrier is feasible if the carrier itself is made of silicon. In addition, however, the carrier would be required to support a high I/O density in order to interconnect the various device chips mounted on it. Greater the granularity of the system, that is, finer the division of the system into sub-units or chips, greater will be the number of I/Os required. It is expected that such I/O densities will necessitate bonding pads that are on the order of 5 to 10 &mgr;m size and spaces which are presently outside the realm of possibility of typical packaging I/O pads which are at least 10 to 20 times coarser in size and spacing.
It is therefore highly desirable to enable a microjoining structure to interconnect several chips on to a system-on-a-package carrier to achieve significantly higher input/output density between the chips as compared to the current state-of-the-art.
Concomitantly, a particular need has arisen for temporarily—rather than permanently—interconnecting a collection of devices such as chips involving a high density array of the aforesaid microjoints for the specific purpose of first performing a system-level test and then for performing a “burn in.” This enables one to sort out and combine the good quality chips on to the carrier to form a functional and reliable system on a package.
SUMMARY OF THE INVENTION
A general object of the present invention is to furnish the ability to test and “burn in” device chips that require ultra high pitch I/O pads (down to approximately 2.5 &mgr;m on 5 &mgr;m centers).
Another object of the present invention is to realize the ability to test devices that are to be tested and burned in as a part of a collection of devices that form a functional system.
The ability to do all of the above is achieved without forming a permanent metallurgical joint to the devices. This eliminates the need to apply forces to the microjoints to remove bad chips from the test substrate, which is particularly important for these very small sized joint structures.
The test carrier of this invention is reusable for many test cycles since no permanent bonds are formed with the parts that are tested on it. A sorting of the devices that have been tested is carried out based on their level of performance under the test conditions, and particularly is based on a suitable metric (e.g. device speed at the system level).
In fulfillment of the above stated objects, and the particular need noted that has arisen in this art, the present invention, briefly stated, provides a structure comprising a system level test and burn in carrier, said structure comprising: a system for testing an array of device chips by temporarily attaching a microjoint structure, comprising a carrier, to the array, the carrier being a multilayer substrate having a plurality of receptacles provided with dendritic surface features, said receptacles matching a pattern and size of microjoint pads on the device chips; test pads; interconnect wiring that connects the test pads to the dendritic receptacle array, and interconnect wiring additionally providing connections between a multiplicity of the devices mounted on the carrier so as to form a complex functional system that can be adequately tested while on the carrier.
In accordance with the process of the present invention, the device chips to be tested and burned in are provided with microjoint connection metallurgies according to related dockets YOR . . . 0216 and YOR . . . 0217. Then with application of a conformal pressure the device pads are pushed against the dendritic contacts on the carrier so as to establish a reliable temporary electrical connection for the duration and conditions of a typical test and burn in process. At the end of this regimen, any bad quality chips are removed and replaced with new chips. The regimen iteratively leads to a final collection of chips deemed to be functional at a system level with a good degree of reliability.
The foregoing and still further objects and advantages of the present invention will be more apparent from the following detailed explanation of the preferred embodiments of the invention in connection with the accompanying drawing.
REFERENCES:
patent: 5137461 (1992-08-01), Bindra et al.
patent: 5420520 (1995-05-01), Anschel et al.
patent: 6339024 (2002-01-01),
Magerlein John Harold
McKnight Samuel Roy
Petrarca Kevin Shawn
Purushothaman Sampath
Sambucetti Carlos Juan
Ohlandt Greeley Ruggiero & Perle L.L.P.
Pert Evan
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