Tap time division multiplexing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S701000

Reexamination Certificate

active

11015330

ABSTRACT:
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

REFERENCES:
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patent: 5214760 (1993-05-01), Hammond et al.
patent: 5319754 (1994-06-01), Meinecke et al.
patent: 5381348 (1995-01-01), Ernst et al.
patent: 5627842 (1997-05-01), Brown et al.
patent: 5640521 (1997-06-01), Whetsel
patent: 5845059 (1998-12-01), McClure
patent: 6023778 (2000-02-01), Li
patent: 6347063 (2002-02-01), Dosaka et al.
patent: 2003/0101376 (2003-05-01), Sanghani

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