Tantalum barrier layer for copper metallization

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S643000, C438S687000

Reexamination Certificate

active

06953742

ABSTRACT:
A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.

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Yamagihshi et al., “TEM/SEM Investigation and Electrical Evaluation of a Bottomless 1-PVS Ta(N) Barrier in a Dual Mask”,Advanced Metallization Conference 2000, Proceedings of the Conference 2000, Advanced Metallization Conference 2000, Proceedings of the Conference, San Diego, CA, USA, Oct. 2-5, 2000, 279-285 pp.

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