Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-10-11
2005-10-11
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S643000, C438S687000
Reexamination Certificate
active
06953742
ABSTRACT:
A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.
REFERENCES:
patent: 5770519 (1998-06-01), Klein et al.
patent: 5846332 (1998-12-01), Zhao et al.
patent: 5933753 (1999-08-01), Simon et al.
patent: 5985762 (1999-11-01), Geffken et al.
patent: 6100587 (2000-08-01), Merchant et al.
patent: 6106625 (2000-08-01), Koai et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6265313 (2001-07-01), Huang et al.
patent: 6277249 (2001-08-01), Gopalraja et al.
patent: 6284657 (2001-09-01), Chooi et al.
patent: 6287977 (2001-09-01), Hashim et al.
patent: 6294458 (2001-09-01), Zhang et al.
patent: 6306732 (2001-10-01), Brown
patent: 6328871 (2001-12-01), Ding et al.
patent: 6368954 (2002-04-01), Lopatin et al.
patent: 6391785 (2002-05-01), Satta et al.
patent: 6498091 (2002-12-01), Chen et al.
patent: XP-002223600 (2000-05-01), None
patent: 2000-323571 (2000-11-01), None
Yamagihshi et al., “TEM/SEM Investigation and Electrical Evaluation of a Bottomless 1-PVS Ta(N) Barrier in a Dual Mask”,Advanced Metallization Conference 2000, Proceedings of the Conference 2000, Advanced Metallization Conference 2000, Proceedings of the Conference, San Diego, CA, USA, Oct. 2-5, 2000, 279-285 pp.
Cao Wei
Chen Ling
Ganguli Seshadri
Marcadal Christophe
Applied Materials Inc.
Guenzer Charles S.
LandOfFree
Tantalum barrier layer for copper metallization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Tantalum barrier layer for copper metallization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tantalum barrier layer for copper metallization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3491830