System-on-chip (SOC) having built-in-self-test circuits and...

Details System-on-chip (SOC) having built-in-self-test circuits and... System-on-chip (SOC) having built-in-self-test circuits and...

2005-02-25

2008-09-02

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07421635

ABSTRACT:
A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

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Lobetti-Bodoni, M.; Pricco, A.; Benso, A.; Chiusano, S.; Prinetto, P. “An on-line BISTed SRAM IP core”. Test Conference, 1999. Proceedings., International. Sep. 28-30, 1999 pp. 993-1000.
English abstract of corresponding PCT application WO 02/095586 A2 provided).

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