System level in-situ integrated dielectric etch process...

Details System level in-situ integrated dielectric etch process... System level in-situ integrated dielectric etch process...

2000-03-29

2002-12-31

Hiteshew, Felisa (Department: 1765)

Etching a substrate: processes

Gas phase etching of substrate

Etching inorganic substrate

C216S041000, C216S067000, C438S724000, C438S725000, C438S732000, C438S740000

Reexamination Certificate

active

06500357

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to plasma etch processes used in the manufacture of semiconductor integrated circuits. More specifically, the present invention relates to a system level in situ integrated process for etching layered dielectric structures serving as inter-level dielectric layers.
The technology of fabricating semiconductor integrated circuits continues to advance in the number of transistors, capacitors and other electronic devices that can be fabricated on a single integrated circuit chip. This increasing level of integration is being accomplished in large part by decreasing the minimum feature sizes of the integrated circuits. The increasing level of integration has also resulted in an increase in the number of layers that make up the integrated circuit. Even as the number of layers in the integrated circuit continues to increase, advanced processes are being developed which allow for a reduction in the number of processing steps for a functional layer. However, these advanced processes often make extraordinary demands upon the chemistry of the etching process. Dielectric etching has presented some of the most difficult demands.
In the past the common materials for inter-level dielectric have been based upon silicon-based oxide materials that serve as electrical insulators, such as undoped silicon oxide, fluorine-doped silicon oxide and other related materials. Recently, interest has developed in insulating materials with even lower dielectric constants (e.g., low-k dielectrics with a k value less than 3), some of which are based upon silicon but others are based upon carbon.
Many advanced integrated circuits contain multiple wiring layers separated from the silicon substrate and from each other by respective dielectric layers. Particularly logic circuitry, such as microprocessors, employ several layers of metallization with intervening inter-level dielectric layers. Small via holes need to be etched through each of the dielectric layers. The via holes are then filled with a conductor, composed typically of aluminum or tungsten in the past but more recently composed of copper. A horizontal wiring layer is formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. The conventional process not only fills the via holes but also overfills them to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photoresist layer over the planar metal layer and etches the exposed metal into a network of conductive interconnects.
In contrast, a recently developed damascene process substitutes chemical mechanical polishing for metal etching. A dual damascene structure, as illustrated in sectioned isometric view of
FIG. 1
, has been proposed for advanced chips which avoids the metal etching and combines the metallization of the via and horizontal interconnect. There are two general types of dual damascene processes, self-aligned and counterbore, both of which produce the structure of FIG.
1
.
A substrate
10
includes a conductive feature
11
in its surface. If substrate
10
already includes a wiring level at its surface, the conductive feature
11
is metallic and may be a previously formed dual damascene metallization. The interconnection between two metallic wiring levels is called a via. Conventionally, the metal forming the metallization has been aluminum and its alloys or tungsten, but many advanced integrated circuits are now being designed with copper metallization. Alternatively, conductive feature
11
may be a doped region in silicon substrate
10
, for example, a source or drain. In this case, the interconnection between the silicon layer and a first metallization layer is called a contact. Although some aspects of the present invention apply to contacts, the major portion of the disclosure and the details of the invention are directed to vias, particularly copper vias and underlying copper lines
11
.
A lower stop layer
12
, a lower dielectric layer
14
, an upper stop layer
16
, and an upper dielectric layer
20
are deposited over substrate
10
and included conductive feature
11
. Stop layers
12
,
16
have compositions relative to those of dieleric layers
14
,
20
such that an etch chemistry is available which effectively etches a vertical bole in the overlying dielectric layer
14
,
20
but stops on the stop layer
12
,
16
. That is, the etch selectively etches the dielectric layer over the stop layer. Alternatively stated, the dielectric etch is selective to the stop material. As mentioned before, more advanced circuits are being designed with the two dielectric layers
14
,
20
being composed of a dielectric material having a lower dielectric constant than that of silicon dioxide. However, the specific examples of the invention described here use undoped silicon oxide, related non-stoichiometric materials SiO
x
, and related doped silica glasses for the dielectric, such as fluorinated silica glass (FSG), e.g., F-TEOS which exhibits much the same chemistry as SiO
2
. These materials will be hereafter collectively be referred to a oxides. The typical stop material for oxide is silicon nitide (Si
3
N
4
) although non-stoichiometric ratios SiN
x
are included where x may be between 1.0 and 1.5. These materials will hereafter be referred to as nitrides. An advantage of the combination of oxide and nitride is that both materials can be grown in a single reactor by plasma-enhanced chemical vapor deposition (PECVD). For example, silicon oxide can be grown under PECVD using tetraorthosilicate (TEOS) as the main precursor gas. Silicon nitride can be grown in the same reactor using silane as the main precursor in the presence of a nitrogen plasma. These examples are non-limiting and simply show the advantage of the illustrated vertical structure.
The dual damascene etch structure shown in
FIG. 1
is formed in the previously described vertical structure.
FIG. 2
is a flowchart illustrating one processing sequence that can be performed to etch the dual damascene structure shown in FIG.
1
. As shown in
FIG. 2
, after all the dual damascene layers
12
,
14
,
16
,
20
are grown in a horizontally unpatterned vertical structure (step
74
), a photoresist layer (not shown) is deposited over upper oxide layer
20
and patterned with apertures corresponding to the via holes
18
(step
76
). Next an extended via hole is etched from the top of upper oxide layer
20
to the top of lower nitride stop layer
12
using a multistep etch process that must etch very deeply, for example, 2.5 &mgr;m through a very narrow hole (e.g., hole widths of 0.25 or 0.18 &mgr;m). This multistep etch process (step
78
) is rather demanding and must take the possibility of etch stop into consideration. (Etch stop arises from the fact that the high selectivity of fluorocarbon-based oxide etches to underlying silicon or silicon nitride as well as verticality of the side walls depend upon a polymer depositing on non-oxide surfaces and on the side walls. However, if the etching chemistry is too rich, favoring too much polymer formation, the polymer bridges the sidewalls and covers the oxide bottom of he developing hole and prevents further etching.) Earlier steps in this multistep etch process must etch through both the upper oxide layer and the upper nitride etch stop layer while the final step of the process requires good selectivity to underlying lower nitride stop layer
12
. Two examples of single chamber, in situ processes suitable for etch step
78
are presented in U.S. application Ser. No. 09/201,590, entitled “In situ Dielectric Etch Process for IC Structures Using Copper Interconnects,” having co-inventors Hung et al. and assigned to Applied Materials, the assignee of the present invention.
At the completion of multistep etch
78
, a photoresist layer (not shown in
FIG. 1
) is deposited over the top of the upper oxide layer
20
and patterned to

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