System for reducing silicon-consumption through selective...

Details System for reducing silicon-consumption through selective... System for reducing silicon-consumption through selective...

2002-04-24

2003-10-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S197000, C438S585000, C438S655000, C438S683000

Reexamination Certificate

active

06630394

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor device fabrication, and more specifically, to a system for forming a disilicide region to reduce consumption of underlying silicon.
BACKGROUND OF THE INVENTION
Since the invention of integrated circuits, the number of devices on a chip has grown at a near-exponential rate. The fabrication methods of the semiconductor industry have been modified and improved continuously for almost four decades. With each improved method, the capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices. Future improvements will require integrated circuit devices such as transistors, capacitors, and connections between devices to become even smaller and more densely populated on the chip.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. The requirements of high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any functional degradation. Increased packing density of the integrated circuits is usually accompanied by smaller feature size.
Transistors, or more particularly, metal oxide semiconductor field effect transistors (MOSFET), are important and frequently employed devices. The MOSFET is commonly used in integrated circuits because of its desirable performance characteristics. However, sub-micron scale MOSET's are prone to problems such as junction punchthrough, current leakage, and contact resistance, which cause reduced yield and reliability. Further, connections between such transistors must also have smaller dimensions, or similar problems may occur throughout the circuit.
Semiconductor device fabrication often uses a self-aligned silicidation process (SALICIDE). In a silicidation process, a metal (e.g., titanium) is placed into contact with silicon and heated. Heating of the metal and silicon causes the two to combine to form a silicide compound. Silicidation is conventionally used to provide a conductive contact between silicon in a semiconductor device and a metal contact, which may be connected to a conductive lead. The resulting silicon-silicide-metal combination provides lower contact resistance than a direct metal-to-silicon contact. Large contact resistance is generally detrimental to the performance of a semiconductor device.
A problem with the use of titanium as the metal in a silicide compound is that titanium silicide suffers from various size effects. As the volume of a titanium silicide region in a semiconductor device decreases, its contact resistance increases. Thus, as semiconductor devices shrink, particularly the length of a gate in a semiconductor device, the use of titanium silicide has become unacceptable due to resulting high contact resistances. Because of the susceptibility to size effects of titanium silicide, cobalt and nickel are sometimes used as alternatives. In contrast to titanium silicide, cobalt silicide and nickel silicide do not suffer size effects and have a relatively constant resistance for varying volumes of the resulting silicide compound.
Titanium silicide, although widely used in 0.25 um and above device applications, is not suitable for fabricating sub-0.25 um devices. Nickel silicide is desirable for sub-0.25 um devices because it is independent of line width. Nickel silicide, however, is the least stable silicide. Cobalt silicide is independent of line width and is stable for the thermal budget used in most devices. Cobalt silicide formation does, however, consume the most silicon of all the silicides. This consumption limits the use of cobalt silicide as junctions become shallower because of increased packing density.
A conventional salicide fabrication process is depicted in
FIGS. 1A-1E
. A semiconductor device
10
is formed on silicon substrate
12
.
FIG. 1A
depicts semiconductor device
10
during an initial state of construction after formation of a source region
14
and a drain region
16
in a substrate
12
and after formation of a gate body
18
overlying an oxide layer
20
. Also depicted in
FIG. 1A
are thick field oxide regions
22
used to isolate the resulting semiconductor device
10
from adjacent semiconductor devices. Source region
14
, drain region
16
, gate body
18
, oxide layer
20
, and field oxide regions
22
may be formed according to conventional techniques.
One example of a conventional technique for forming the semiconductor device
10
depicted in
FIG. 1A
is described below. In this example, substrate
12
is a P-type silicon substrate; however, substrate
12
could be an N-type substrate. Thick field oxide regions
22
are formed by local oxidation of silicon using a process such as that shown in Havemann, et al. U.S. Pat. No. 4,541,167, issued Sep. 17, 1985 and assigned to the assignee of this application. Substrate
12
is then subjected to a thermal oxidation in a steam environment for approximately 7 minutes at a temperature of approximately 850° C. to form oxide layer
20
as shown in FIG.
1
A. Oxide layer
20
may be grown to a thickness of approximately 3 to 10 nanometers, however, other thicknesses for oxide layer
20
may be used. A polysilicon layer is then deposited, patterned and etched using conventional photolithographic techniques to form polysilicon gate body
18
. A thickness of polysilicon gate body is approximately 400 nanometers. Appropriate ions
19
are then implanted, self-aligned aligned to form source region
14
and drain region
16
. For a P-type substrate, appropriate ions include phosphorous ions and arsenic ions. A typical implantation includes implantation of arsenic ions at a density of approximately 3×10
5
ions per square centimeter and an energy of approximately 150 kiloelectron volts. A second ion implantation of phosphorous ions having a density of approximately 4×10
14
ions per square centimeter and an energy level of approximately 85 kiloelectron volts may also be incorporated.
A channel region is defined within substrate
12
between source region
14
and drain region
16
. Although particular details of the formation of source region
14
, drain region
16
, gate body
18
, oxide layer
20
, and field oxide regions
22
have been provided, other methods and techniques are used.
FIG. 1B
depicts semiconductor device
10
after formation of a gate oxide layer
24
and sidewall spacers
26
and
28
. Gate oxide layer
24
is formed by patterning and etching oxide layer
20
using conventional photolithographic techniques. Sidewall spacers
26
and
28
provide separation between a silicide that will be formed over source and drain regions
14
,
16
and gate body
18
, which is electrically conductive. Sidewall spacers
26
and
28
may be formed, for example, by depositing a conformal layer of TEOS oxide over semiconductor device
10
and anisotropically etching the TEOS oxide layer, which leaves sidewall spacers
26
and
28
. Sidewall spacers
26
and
28
may alternatively be formed prior to implantation of ions
19
to form source region
14
and drain region
16
.
FIG. 1C
depicts the deposition of a thin buffer layer
30
of metal. Thin buffer layer
30
acts as a buffer layer between silicon in source region
12
, drain region
14
, and gate body
18
and a metal layer during formation of silicide regions in semiconductor device
10
. Zirconium and hafnium are both particularly suitable metals for thin buffer layer
30
; however, other suitable metals are used. Thin buffer layer
30
is deposited outwardly from semiconductor device
10
to a thickness of approximately 1 to 5 nanometers. Thin buffer layer
30
resists spiking during the formation of a silicide and also contributes to low contact resistance between a resulting silicide and a metal contact. Although particular thicknesses for thin buffer layer
30
have been described, o

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